Op Amp Input Offset Voltage

In short: Input offset voltage (V_OS) is the tiny differential DC voltage you must apply between an op-amp's inputs to force its output to zero, and it is minimized by external/trim nulling for a fixed value or by auto-zero/chopper architectures that continuously cancel the error and its temperature drift.

Every real operational amplifier departs from the perfect device described in ideal op-amp characteristics. One of the most consequential departures for precision analog design is the input offset voltage. It looks small on a datasheet, but in a high-gain DC path it can swamp the signal you actually care about. This article explains where V_OS comes from, why it drifts with temperature, and the two families of techniques, static nulling and dynamic chopping, that modern parts use to beat it down to the microvolt level.

What input offset voltage actually is

Ideally, shorting an op-amp's two inputs together drives the output to exactly 0 V (for a split supply). In practice the output slams to a rail. The input offset voltage is defined as the equivalent differential voltage you would have to inject at the input to bring the output back to zero. Referred-to-input (RTI) is the standard way to quote it, because the output error is simply V_OS multiplied by the noise gain.

Consider a non-inverting amplifier with a gain of 1000 (noise gain 1000) built from a jellybean part with V_OS = 2 mV. The output carries a DC error of 2 mV × 1000 = 2 V before any signal arrives. For a thermocouple front end measuring tens of microvolts, that is catastrophic. Swap in a precision auto-zero part with V_OS = 2 µV and the same gain yields only 2 mV of error.

Key fact: Output DC error = V_OS × noise gain. A 1 mV offset in a ×100 stage becomes 100 mV at the output, regardless of signal amplitude.

Where the offset comes from

The dominant source is mismatch in the input differential pair. In a bipolar (BJT) input stage, V_OS is driven largely by mismatch in the base-emitter voltage, which in turn traces back to differences in saturation current (emitter area, doping) and collector-current imbalance set by load-resistor mismatch. In a CMOS or JFET input stage, the culprit is threshold-voltage (V_TH) mismatch and transconductance (W/L) mismatch between the differential pair devices.

Because mismatch scales inversely with the square root of device area (Pelgrom's law), designers simply draw bigger, well-matched, common-centroid input transistors when they want low offset, trading die area for precision. Typical untrimmed values: CMOS general-purpose ~1-10 mV, trimmed bipolar precision ~25-100 µV, chopper/auto-zero ~1-5 µV.

Temperature drift: the parameter that trimming can't fully fix

A one-time trim at 25 °C sets V_OS to near zero at that temperature, but offset changes as the die heats or cools. This is the input offset voltage drift, quoted in µV/°C (the datasheet symbol is usually ΔV_OS/ΔT or TCV_OS).

Drift matters because a trimmed part with 10 µV/°C over a 100 °C industrial range can wander by 1 mV, erasing the benefit of the trim. Worse, V_BE mismatch and the trim resistors themselves have their own temperature coefficients, so zeroing offset at room temperature can actually leave a non-zero slope. This is why high-precision parts specify drift as a guaranteed maximum, and why auto-zero techniques, which re-null continuously, dominate the sub-1-µV/°C class.

Static nulling: external and factory trim

Classic parts such as the OP07 and older 741 expose dedicated offset-null pins. You wire a 10 kΩ potentiometer across the null terminals (tied to V−), short the inputs, and adjust until the output reads zero. The pot imbalances the input stage's collector loads to cancel the intrinsic mismatch. It works, but it fixes only the room-temperature value, does nothing for drift, and ages.

Modern precision bipolar parts move the trim inside: during wafer test, a laser physically trims thin-film resistors (or blows zener/fuse links) to null V_OS at 25 °C. This removes the external pot and board real estate but shares the same fundamental limitation, it is a single-point correction that leaves the temperature slope behind.

Dynamic cancellation: chopper and auto-zero amplifiers

The elegant modern answer is to measure the offset while the amplifier runs and subtract it continuously. Two closely related schemes do this.

Chopper amplifiers modulate the DC input up to a chopping frequency (tens to hundreds of kHz) using a switch network, amplify it where the amplifier's own offset and 1/f noise live only at DC, then demodulate back down. The amplifier's offset, being at DC, does not survive the second chopping step, so it is rejected along with low-frequency flicker noise. Auto-zero amplifiers instead use a sampling phase: the amplifier periodically disconnects from the signal, measures its own offset, stores the correction on a capacitor, and applies it during the amplify phase. Most commercial "zero-drift" parts combine both ideas (chop-stabilized auto-zero) to reach V_OS of ~1 µV and drift near 0.01 µV/°C.

Key fact: Chopping converts the offset problem into a noise-and-ripple problem. Zero-drift parts trade near-zero V_OS for switching ripple at the chop frequency, which the output filtering or internal notch filter must handle.

In design flows, you verify offset contribution early: a DC operating-point and Monte Carlo mismatch analysis in a SPICE simulator (Cadence Spectre, Synopsys HSPICE/PrimeSim, or Siemens Eldo/AFS) sweeps device mismatch to predict the V_OS distribution before tape-out, exactly the kind of flow taught in hands-on analog programs at Avecas analog design services.

Practical selection guidance

• Need DC accuracy under a few hundred microvolts over temperature? Reach for a zero-drift/chopper part, not an external null pot.
• Watch the AC consequences: chopper ripple and intermodulation can land in your band; add a low-pass filter or pick a part with an internal ripple-reduction loop.
• Remember total DC error also includes input bias current times source resistance; balance the source impedances seen by both inputs.
• For a refresher on the surrounding parameters, revisit our note on CMRR and PSRR in op-amps.

Go deeper: Our CourseTron Analog IC Design course walks you from differential-pair mismatch math through building a chop-stabilized amplifier in a real simulator, with Monte Carlo labs and interview drills.

Frequently asked questions

Is input offset voltage the same as output offset?

No. V_OS is referred to the input. The output offset is V_OS multiplied by the circuit's noise gain, so the same input offset produces a far larger error in a high-gain stage.

Why can't I just trim offset once and forget it?

A single trim cancels V_OS only at the trim temperature. The underlying mismatch has a temperature coefficient, so the offset drifts as the die heats, which is why drift (µV/°C) is specified separately.

What is a "zero-drift" op-amp?

A marketing term for chopper or auto-zero architectures that continuously self-null, achieving V_OS around 1 µV and drift near 0.01-0.05 µV/°C, far better than any one-time trim.

Do CMOS or bipolar inputs have lower offset?

Untrimmed bipolar pairs usually match better than CMOS because V_BE mismatch is smaller than V_TH mismatch. However, trimming and chopping largely erase the distinction in modern precision parts.