In short: The non-inverting op-amp applies the input to the + terminal and feeds a fraction of the output back to the – terminal, giving a positive gain of 1 + Rf/Rg together with an enormous (ideally infinite) input impedance that the inverting topology can never match.
The non-inverting amplifier is one of the two canonical op-amp building blocks every analog engineer draws from memory. It takes the signal directly on the non-inverting (+) input, produces an in-phase, scaled copy at the output, and — because the source looks straight into the op-amp's input terminal — barely loads whatever drives it. That single property makes it the default choice for buffering sensors, ADC drivers, and any high-impedance node where the inverting configuration would be a liability.
The circuit and the negative-feedback idea
Picture an ideal op-amp. Two rules govern it when negative feedback is present: (1) the two inputs settle to the same voltage — the "virtual short" — and (2) no current flows into either input. The signal Vin enters the + terminal. A resistor divider made of Rf (output to – node) and Rg (– node to ground) samples the output and returns a fraction of it to the – terminal.
Deriving the gain from feedback
Apply the two rules. Because no current enters the – input, Rf and Rg form a simple divider from Vout to ground, so the voltage at the – node is:
V− = Vout · Rg / (Rf + Rg)
The virtual short forces V− = V+ = Vin. Substitute and solve for Vout:
Vin = Vout · Rg/(Rf+Rg) ⟹ Av = Vout/Vin = 1 + Rf/Rg
The +1 term is the signature of the non-inverting amplifier. The gain can never drop below unity — set Rf = 0 (or Rg = ∞) and you get the voltage follower, a buffer with gain exactly 1.
A concrete example: with Rf = 9 kΩ and Rg = 1 kΩ, the gain is 1 + 9 = 10 (20 dB). Feed in a 100 mV sine and you get 1 V out, in phase. Compare that with the inverting amplifier's −Rf/Rg, where the same resistors give −9, an inverted output of 9× — note the inverting circuit cannot produce gains below 1 in magnitude without attenuating, and it inverts phase.
Input impedance: where the two topologies diverge
This is the headline difference. In the non-inverting amplifier the source drives the + terminal directly. For an ideal op-amp that terminal draws no current, so the input impedance is effectively infinite; for a real device it is set by the common-mode input resistance and bias current. A JFET-input part like the Texas Instruments TL072 presents on the order of 1012 Ω, and a CMOS precision part such as the Analog Devices AD8220 reaches 1013 Ω or more.
In the inverting amplifier, by contrast, the + input is grounded and the signal enters through Rin into the virtual-ground summing node. The source therefore sees an input impedance equal to Rin — typically a few kΩ. A 10 kΩ sensor driving a 1 kΩ inverting input loses roughly 90% of its signal to the divider before amplification even begins.
| Property | Non-inverting | Inverting |
|---|---|---|
| Gain | 1 + Rf/Rg | −Rf/Rin |
| Phase | In phase (0°) | Inverted (180°) |
| Input impedance | Very high (≈ op-amp Zin) | ≈ Rin (finite, low) |
| Min |gain| | 1 (buffer) | can be <1 (attenuate) |
| Virtual ground at – | No (follows Vin) | Yes (held at 0 V) |
Rule of thumb: when the source is high-impedance (piezo sensor, pH electrode, photodiode transimpedance follow-on), reach for the non-inverting or buffer configuration so you do not attenuate the signal before you amplify it.
Real-world non-idealities
The 1 + Rf/Rg formula assumes infinite open-loop gain and infinite bandwidth. In practice the closed-loop bandwidth is bounded by the gain-bandwidth product (GBW). A part with 10 MHz GBW configured for a gain of 10 gives roughly 1 MHz of bandwidth — f−3dB ≈ GBW / Av. Input offset voltage multiplies by the noise gain (also 1 + Rf/Rg), so a 1 mV offset at a gain of 100 appears as 100 mV of DC error at the output. When you model these in SPICE — whether Cadence Spectre, Synopsys HSPICE, or Siemens' Eldo — use the manufacturer's macromodel rather than an ideal source to capture GBW, slew rate, and bias-current effects.
Bias-current error is worth a design note: match the DC resistance seen by both inputs (add a resistor equal to Rf‖Rg in series with the + input) so the bias currents produce cancelling drops. For the design-services side of taking such a stage to silicon or board, teams often lean on partners like Avecas analog design services to close GBW, noise, and layout trade-offs.
Where you will use it
Non-inverting stages anchor three-op-amp instrumentation amplifiers, ADC driver front-ends, active filter sections (Sallen-Key uses a non-inverting gain block), and sensor buffers. Any time the previous stage cannot source current, the near-infinite input impedance is the deciding factor. For a side-by-side treatment of the sign-flipping sibling, see our companion piece, and for the loading math in detail, our op-amp loading guide.
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Frequently asked questions
Why is the non-inverting gain always at least 1?
Because the formula is 1 + Rf/Rg and both resistors are positive, the minimum occurs when Rf = 0, giving unity. The input is passed straight through plus whatever the feedback divider adds, so you can never attenuate.
Is the input impedance truly infinite?
No — it is very high but finite, set by the op-amp's common-mode input resistance, input capacitance, and bias current. Bipolar-input parts are lower (MΩ range); JFET and CMOS inputs reach 1012–1013 Ω.
When should I choose inverting instead?
Choose inverting when you need a phase inversion, a summing junction for multiple inputs, a gain magnitude below 1, or a precisely defined (low) input impedance — for example as a defined termination or in a virtual-ground current-to-voltage converter.
Does the feedback resistor value affect gain accuracy?
Only the ratio Rf/Rg sets the gain, so matched-ratio resistor networks give the best accuracy. Absolute values affect noise and bias-current error, not the ideal gain.