In short: Bias a MOSFET in saturation with a fixed drain current, and a tiny gate-voltage change produces a drain-current change of gm times that amount, which the drain resistor RD turns into an inverted output voltage with gain Av = -gm·RD.
Why a transistor amplifies at all
A MOSFET is a voltage-controlled current source. Put the gate a little higher and more current flows from drain to source. That alone is not amplification, because current is not voltage. Amplification appears when you pass that current through a resistor: Ohm's law converts the current wiggle into a voltage wiggle, and if the resistor is large enough, the output swing is bigger than the input swing. The device did not create energy; the supply did. The transistor only steers how much of the supply's energy lands on the output.
The catch is that the transistor behaves as a good, predictable current source only in one region: saturation. In triode it acts like a resistor, and in cutoff it does nothing. So the whole job of "biasing" is to park the device in saturation, with a known current, so the small signal can ride on top. This is the single most asked analog interview question for freshers, and most people stumble because they memorise the gain formula without knowing where it breaks.
Biasing for saturation: the numbers
An NMOS is in saturation when VGS > Vth and VDS ≥ VGS − Vth, where VGS − Vth is the overdrive voltage Vov. In that region the square-law model gives ID = ½·k·(W/L)·Vov², with k = µCox. Let us design a concrete stage in a generic 180 nm-style process with VDD = 1.8 V.
- Target drain current: ID = 0.5 mA.
- Choose Vov = 0.2 V (a sensible compromise between speed and efficiency).
- With Vth = 0.45 V, the gate bias is VG = 0.65 V (source grounded).
- Choose RD = 2 kΩ, so the DC drop is 0.5 mA × 2 kΩ = 1.0 V and the drain sits at VD = 0.8 V.
- Saturation check: VDS = 0.8 V is greater than Vov = 0.2 V, so the device has 0.6 V of headroom.
Key fact: the drain should rest roughly in the middle of the allowed range, between Vov (the saturation edge) and VDD, so the output can swing both ways before the transistor falls into triode or cuts off.
Deriving gm and the gain
Now perturb the gate by a small vin. The drain current changes by id = gm·vin, where gm = ∂ID/∂VGS at the bias point. Differentiating the square law gives three equivalent forms:
- gm = k·(W/L)·Vov
- gm = 2·ID / Vov
- gm = √(2·k·(W/L)·ID)
Using our numbers: gm = 2 × 0.5 mA / 0.2 V = 5 mS. The extra current flows through RD and drops the drain voltage, so vout = −id·RD = −gm·RD·vin. Therefore:
Av = vout / vin = −gm·RD = −5 mS × 2 kΩ = −10
The minus sign is real: when the gate rises, the current rises, the drop across RD grows, and the drain falls. A common-source stage is an inverting amplifier. A 10 mV peak input becomes a 100 mV peak output centred on 0.8 V.
Real devices have channel-length modulation. The output resistance ro ≈ 1/(λ·ID) appears in parallel with RD, giving Av = −gm·(RD ∥ ro). With λ = 0.1 V⁻¹, ro = 1/(0.1 × 0.5 mA) = 20 kΩ, so RD ∥ ro = 1.82 kΩ and the gain drops to about −9.1. This is the small-signal view; for the full hybrid model see our guide to the MOSFET small-signal model.
Key fact: the intrinsic gain gm·ro = 2/(λ·Vov) is the ceiling for any single transistor, whatever load you use. Lowering Vov raises it, but at the cost of speed and sensitivity to mismatch.
Watching the signal ride the bias
The animation below shows the idea in motion: a small sine wave on the gate becomes a taller, flipped sine wave at the drain. Both ride on their own DC levels, which is exactly what the bias network establishes.
Practical limits and trade-offs
The formula Av = −gm·RD suggests you could just make RD huge. You cannot. The DC drop ID·RD must leave the device in saturation, so RD is capped by the headroom: here, ID·RD ≤ VDD − Vov = 1.6 V, i.e. RD ≤ 3.2 kΩ at 0.5 mA. At that limit the drain sits at the edge of triode and any swing clips. Practical designs stop well short, which is why a gain of roughly 10 to 15 is the comfortable region for this resistive-load stage.
| Knob | Effect on gain | Cost |
|---|---|---|
| Increase ID (fixed W/L) | gm rises as √ID | Power, less headroom across RD |
| Increase W/L (fixed ID) | gm rises as √(W/L), Vov falls | Area, capacitance, weak-inversion drift |
| Increase RD | Gain rises linearly | Headroom, bandwidth, thermal noise |
| Raise channel length L | ro rises, less λ loss | Speed and area |
Bandwidth is the other casualty. The output pole sits at about 1/(2π·RD·CL), so doubling RD doubles the gain and halves the bandwidth: a fixed gain-bandwidth trade you will meet in every analog design review. This is also why industrial designs replace RD with an active load such as a PMOS current source, buying gain of 50 to 200 without eating voltage headroom.
In industry, you would not trust hand maths alone. Cadence Virtuoso with Spectre, Synopsys HSPICE or CustomExplorer, and Siemens Eldo all report gm, gds, Vdsat and a saturation-margin flag per device from the DC operating-point analysis. A common signoff step is to sweep PVT corners and confirm every transistor keeps a positive margin, since a slow, cold corner can push Vth up and shrink your Vov. Teams doing this professionally often get design support from partners such as Avecas design services.
Key fact: always set bias with a current reference or a ratio (a current mirror), not a bare resistor divider on VG. Vth moves tens of millivolts across temperature and process, which at square-law sensitivity can move ID by 20% or more.
Common interview traps
- Using gm = µCox(W/L)Vov for a short-channel device. Velocity saturation makes ID closer to linear in Vov, so gm flattens; measure it from simulation instead.
- Forgetting the load in a cascade. The next stage's input resistance and capacitance load RD; infinite for MOS at DC, but not at speed.
- Forgetting the sign. Say "inverting" in the answer; interviewers listen for it.
- Ignoring body effect or source degeneration. With a source resistor RS the gain becomes −gm·RD / (1 + gm·RS), trading gain for linearity.
To go deeper into the equivalent-circuit view, read the sibling guide on the common-source amplifier biasing techniques. If you want a mentor-led route into analog layout and training, the team at ChipXpert VLSI training runs hands-on programmes.
Ready to practise this with real simulations? Explore the analog design track in our CourseTron courses and build, bias and measure your own amplifier stage.
Frequently asked questions
Why must the MOSFET be in saturation to amplify?
In saturation the drain current depends mainly on VGS and only weakly on VDS, so the device acts as a controlled current source with a high output resistance. In triode the current depends strongly on VDS, the gain collapses, and the response becomes nonlinear.
What does gm physically represent?
It is the slope of the ID versus VGS curve at the bias point, in siemens (A/V). A gm of 5 mS means every 1 mV on the gate adds 5 µA to the drain current.
Why is the gain negative?
Higher gate voltage increases drain current, which increases the drop across RD, so the drain voltage falls. The output moves opposite to the input, a 180 degree phase shift.
How does channel-length modulation change the result?
The finite output resistance ro appears in parallel with RD, so the gain is −gm·(RD ∥ ro). It reduces gain slightly when RD is small compared to ro, and dominates when you use an active load.