In short: A linear voltage regulator holds its output steady by using a feedback loop that continuously adjusts a series pass transistor so the output tracks a reference, trading power efficiency and heat for low noise and simplicity.
Almost every mixed-signal board you will ever debug has at least one linear voltage regulator quietly doing the unglamorous work of turning a messy, drifting input rail into a clean, predictable supply. Ask an analog interviewer to name a circuit a junior engineer must understand cold, and the linear regulator — and its low-dropout cousin, the LDO — is near the top of the list. This article walks through exactly how it works, why it wastes power, and when that waste is a price worth paying.
The core idea: a controlled resistor in series
A linear regulator is conceptually a variable resistor placed between the input and the load, controlled so that the voltage dropped across it is always exactly the amount needed to keep the output at the target. If the input is 5 V and you want 3.3 V out, the regulator drops 1.7 V. If the load suddenly pulls more current and the output starts to sag, the controller lowers the effective resistance to push the output back up. Nothing is switched on and off — the pass element conducts continuously, which is why the output is so quiet.
The “variable resistor” is really a pass element: a bipolar transistor (NPN, PNP, or Darlington) or a MOSFET operating in its active/linear region. An op-amp-style error amplifier compares a scaled copy of the output against a fixed reference voltage (commonly a bandgap reference near 1.2 V) and drives the pass element's base or gate accordingly. That loop is the whole trick.
Walking the feedback loop
Say the output is set for 3.3 V with a divider that feeds back 1.2 V to the error amplifier's inverting input, matched against the 1.2 V reference. In steady state the two inputs are equal and the loop is balanced. Now a GPU core or an SoC wakes up and the load current jumps from 50 mA to 500 mA. The output momentarily droops, the feedback voltage falls below the reference, the error amplifier's output swings to turn the pass element on harder, and more current flows until the output recovers. The time it takes to recover is the transient response, and it is dominated by the loop bandwidth and the output capacitor's effective series resistance (ESR).
Key fact: Loop gain is what sets regulation accuracy. A regulator with 80 dB of DC loop gain suppresses line and load variation by a factor of ~10,000, which is how a part can hold the output to within a few millivolts across a wide current range.
Dropout: the number that decides everything
Dropout voltage is the minimum input-to-output difference the regulator needs to stay in regulation. Below it, the pass element is fully on and simply passes through whatever the input does. A classic NPN-based regulator like the venerable 7805 needs about 2 V of headroom. A modern LDO built around a PMOS pass device may need only 100–300 mV at full load. That difference matters enormously in battery systems: if you are regulating 3.3 V from a lithium cell that sags to 3.4 V near end-of-life, only an LDO will keep working.
- Standard regulator (NPN/Darlington): dropout 1.5–2 V, robust and stable with almost any output cap.
- LDO (PMOS pass): dropout 0.1–0.3 V, but the pass device sits inside the loop differently and is far pickier about output-cap ESR for stability.
Efficiency and the heat problem
Here is the catch every analog engineer internalizes early: a linear regulator's efficiency is essentially the ratio of output to input voltage, because the pass element carries the full load current while dropping the difference. Efficiency ≈ VOUT/VIN (ignoring quiescent current). Regulating 3.3 V from 5 V gives 66% efficiency at best. Regulating 1.2 V from 12 V gives a dismal 10% — the other 90% becomes heat.
| Scenario | VIN | VOUT | ILOAD | Dissipation | Efficiency |
|---|---|---|---|---|---|
| 5V to 3.3V logic | 5 V | 3.3 V | 500 mA | 0.85 W | 66% |
| 12V to 5V sensor | 12 V | 5 V | 200 mA | 1.4 W | 42% |
| 3.6V to 3.3V (LDO) | 3.6 V | 3.3 V | 300 mA | 0.09 W | 92% |
Power dissipated in the pass element is simply P = (VIN − VOUT) × ILOAD plus a small quiescent term. That heat has to go somewhere, which is where the thermal design comes in. The junction temperature is TJ = TA + P × θJA, where θJA is the package thermal resistance. A SOT-23 part with θJA ≈ 250 °C/W dissipating 0.85 W in a 40 °C ambient would try to reach 252 °C — well past its thermal-shutdown limit. The lesson: linear regulators are only comfortable when the voltage drop is small or the current is modest.
Where linear regulators win
Given the efficiency penalty, why use them at all? Because what they lack in efficiency they repay in cleanliness. A good LDO delivers very low output noise (tens of µVRMS) and high power-supply rejection ratio (PSRR), which is exactly what sensitive analog blocks want. PLLs, ADC/DAC references, RF oscillators, and image sensors are routinely powered by an LDO placed right after a switching converter — the switcher does the bulk step-down efficiently, and the LDO scrubs off the switching ripple. This post-regulator pattern is standard practice; see our deep dive on linear vs switching regulators for when to pick which, and our notes on LDO PSRR and noise budgeting for the layout details that make or break it.
Key fact: Stability of an LDO is a loop-compensation problem. The output capacitor and its ESR place a pole-zero pair in the loop; too little ESR with an older LDO topology can push the phase margin negative and make the output ring. Modern “any-cap” LDOs use internal compensation to tolerate ceramic caps with near-zero ESR.
When you design a custom LDO or integrate one on an SoC, you will verify this behavior in a SPICE environment — Cadence Virtuoso with Spectre for the schematic-level loop gain and stability (STB analysis), or Synopsys HSPICE for Monte Carlo spread on the reference and dropout. Siemens (Analog FastSPICE) is common for larger mixed-signal verification. The loop-gain Bode plot and the load-transient waveform are the two plots an analog reviewer will always ask to see.
Practical selection checklist
- Headroom: Is VIN − VOUT comfortably above the dropout at max load and max temperature?
- Thermal: Compute P and TJ; confirm you stay below thermal shutdown with margin.
- Noise/PSRR: Does the downstream block need the clean rail an LDO provides?
- Output cap: Does the datasheet's stability region match the ceramic cap you intend to use?
- Quiescent current: In always-on battery systems, IQ can dominate standby drain — pick a nano-quiescent LDO.
For teams building this intuition hands-on, our sister training brand ChipXpert's analog design courses run lab sessions on exactly these LDO stability and thermal trade-offs.
Want to design and simulate your own LDO in Cadence Virtuoso, including loop-gain and load-transient verification? Explore CourseTron's hands-on Analog & Power IC design track.
Frequently asked questions
Is an LDO the same as a linear regulator?
An LDO is a type of linear regulator optimized for a very small dropout voltage. All LDOs are linear regulators, but not all linear regulators are low-dropout; a classic 7805 is linear but needs about 2 V of headroom.
Why is a linear regulator inefficient?
Because the pass element carries the full load current while dropping the entire input-to-output voltage difference as heat. Efficiency is roughly VOUT/VIN, so a large step-down is inherently wasteful.
Can I use any output capacitor with an LDO?
No. Older LDOs require a minimum ESR for loop stability and can oscillate with low-ESR ceramics. Always check the datasheet's stable-region plot, or use a modern internally-compensated “any-cap” LDO.
When should I pick a switching regulator instead?
When the voltage drop or current is large enough that linear dissipation becomes unacceptable, or when efficiency and battery life dominate. A common hybrid is a switcher followed by an LDO post-regulator for a clean, efficient rail.