In short: A low-dropout (LDO) regulator is a feedback loop around a pass transistor that trades a small headroom voltage for a quiet, well-regulated rail — and getting its dropout, PSRR, stability, and load-transient response right all comes down to how you size the pass device and place the dominant pole.
An LDO looks deceptively simple: an error amplifier, a reference, a pass transistor, and two feedback resistors. Yet it is one of the most interview-tested analog blocks because every specification pulls the design in a different direction. Push the dropout down and you weaken your PSRR; widen the loop bandwidth for a fast transient and you flirt with instability. This article walks through the five knobs that actually matter and the trade-offs between them, with concrete numbers you can reason about.
The basic topology and the feedback loop
The regulator forces VOUT = VREF × (1 + R1/R2). The error amplifier compares a scaled copy of the output against a clean reference — almost always a bandgap reference circuit that gives ~1.2 V with low temperature drift. The amplifier drives the gate of the pass device so that just enough current flows to hold the output at target. Because it is a closed loop with high DC gain (60–80 dB is typical), load and line errors are divided down by the loop gain.
Dropout voltage and the pass device
Dropout is the minimum VIN − VOUT at which the loop can still regulate. For a PMOS pass device operating deep in the triode region it is simply ILOAD × RDS(on). A 3.3 V rail delivering 300 mA through a 0.5 Ω on-resistance drops 150 mV — comfortably "low dropout." An NMOS or BJT pass device needs a VGS (or VBE) of headroom, pushing dropout to 0.6–1 V unless you add a charge pump to drive the gate above the supply.
Rule of thumb: halving dropout means roughly doubling the pass-device width, which doubles its parasitic gate capacitance and moves the gate pole lower — directly eroding your phase margin.
| Pass device | Typical dropout | Loop note |
|---|---|---|
| PMOS | 50–200 mV | Output pole load-dependent; needs compensation care |
| NMOS (source follower) | 0.5–1 V (unless charge-pumped) | Low output impedance; inherently stable |
| PNP BJT | 0.2–0.5 V | Base current hurts efficiency at light load |
PSRR: keeping supply noise out
Power-supply rejection ratio measures how much ripple on VIN leaks to VOUT. At DC it equals the loop gain, so an 80 dB loop gives 80 dB rejection. But PSRR rolls off as loop gain falls with frequency, and it collapses entirely near the unity-gain crossover — which is exactly where switching-regulator ripple (0.5–2 MHz) often sits. This is why an LDO cascaded after a buck converter is such a common pattern: the buck gives efficiency, the LDO scrubs the ripple.
You verify PSRR in simulation with an AC source stitched into VIN and an .ac sweep in Cadence Spectre or Synopsys HSPICE, reading VOUT/VIN across frequency. Watch the notch-and-recovery shape near crossover; a sagging mid-band PSRR usually points to insufficient loop gain there.
Stability and the dominant pole
The loop has at minimum two poles: one at the error-amplifier output (the high-impedance gate node) and one at VOUT, set by the load resistance and output capacitor. For stability you want one pole clearly dominant so the phase margin at crossover stays above ~45–60 degrees. Two schools exist. Older LDOs rely on the ESR zero of an external electrolytic/tantalum cap to cancel the second pole — hence the dreaded "stability donut" datasheet plot bounding the acceptable ESR range. Modern CMOS LDOs use internal Miller or ahuja compensation so they stay stable with cheap, near-zero-ESR ceramic caps.
Load transient response
When the load jumps — say 10 mA to 200 mA in a few nanoseconds — the loop cannot react instantly. The output capacitor must supply the difference until the amplifier slews the pass-gate. The initial droop is approximately ΔI × (tresponse/COUT) plus the ESR step ΔI × ESR. A 10 µF ceramic output cap with 1 µs loop response and a 190 mA step gives roughly a 19 mV droop from the capacitor term alone. Fast recovery wants high bandwidth and high amplifier slew rate, but both fight the stability margin — the central tension of LDO design.
A useful sanity check: if your load transient overshoots and rings for several cycles, your phase margin is marginal (likely <45°), not just your capacitance. Fix the compensation before you add more output cap.
Teams verifying these numbers at the transistor level lean on tools from Avecas design services and standard flows in Siemens AFS or Cadence Spectre for the transient and stability (STB) analyses before committing to silicon.
Putting it together
Good LDO design is iterative budgeting. Start from the dropout and current spec to size the pass device, confirm the DC loop gain meets your PSRR target, place the dominant pole for 60 degrees of phase margin across the full load range, then stress the load transient and iterate. For a deeper, worked example on the reference that feeds this loop, see our companion piece on the bandgap reference circuit and the broader voltage regulator topologies overview.
Want to design, simulate, and tape out your own LDO with real Cadence and Synopsys flows? Explore CourseTron's analog IC design track on our courses page and build a regulator from spec to GDS.
Frequently asked questions
Why is PSRR worst near the loop crossover frequency?
Because PSRR tracks loop gain, and loop gain falls to unity (0 dB) at crossover. With little gain left to reject it, supply ripple near that frequency passes almost straight through to the output.
Can I always use a ceramic output capacitor?
Only if the LDO is designed for low ESR. Older ESR-compensated parts need a minimum ESR to place a stabilizing zero; a near-zero-ESR ceramic can push them into oscillation. Check the datasheet's stability region first.
PMOS or NMOS pass device for lowest dropout?
PMOS, without extra circuitry, because it can be driven fully into triode so dropout is just I×RDS(on). An NMOS needs its gate driven above the supply (a charge pump) to reach comparable dropout.
How much output capacitance does a fast transient need?
Enough that the capacitive droop ΔI×tresp/C stays within your tolerance, but more cap is not a substitute for adequate phase margin — ringing is a stability problem, not a capacitance one.