JFET vs MOSFET

In short: A JFET controls its channel with a reverse-biased pn junction and is normally ON (depletion-only), while a MOSFET isolates its gate with an oxide, giving near-infinite DC input impedance and the option of enhancement mode; JFETs win on low-frequency noise, MOSFETs win on integration, speed and power.

Two ways to steer one channel

Both devices are voltage-controlled resistors: a gate voltage changes how many carriers can flow between source and drain. The difference is how the gate "talks" to the channel. In a JFET the gate is a heavily doped region forming a pn junction with the channel. In a MOSFET the gate is a conductor separated from the silicon by a thin insulator, typically SiO₂ or, in modern nodes, a high-k hafnium-based stack. That one structural decision explains almost every row in the comparison table later in this article.

Gate structure

Take an n-channel JFET. A lightly doped n-type bar connects source and drain. A p+ gate is diffused on one or both sides. With the gate at zero or negative bias relative to the source, the pn junction is reverse biased and a depletion region extends mostly into the lightly doped channel. Making V_GS more negative widens that depletion region and squeezes the conducting path.

An n-channel MOSFET instead has a polysilicon (or metal) gate over a gate dielectric on a p-type body, with n+ source and drain. There is no junction under the gate. The gate field either repels carriers or attracts them, and a conductive layer forms or does not form at the surface.

Input impedance: why the oxide wins

A reverse-biased silicon junction still leaks. A good small-signal JFET such as the 2N5457 specifies gate leakage of about 1 nA maximum at 25 °C, and typical values are in the pA range. That corresponds to DC input resistance on the order of 10⁹–10¹² Ω. Leakage roughly doubles every 10 °C, so a hot board is much worse. If you forward bias the gate beyond about 0.6 V the junction conducts and the "voltage-controlled" illusion collapses.

A MOSFET gate sees an insulator, so DC gate current is tunnelling or surface leakage only: femtoamps in discrete parts, though in 28 nm and below with ultra-thin oxides, gate leakage is a genuine standby-power concern that high-k metal gate was introduced to tame. The practical limit becomes the capacitance, not resistance: a power MOSFET might present several nF, so the driver must supply charge, not current.

Key fact: Both are "high impedance" at DC, but a JFET gate has a diode in it and can be forward biased; a MOSFET gate is a capacitor and cannot conduct DC at all (until oxide breakdown, roughly 10 MV/cm).

Depletion vs enhancement operation

The JFET is inherently a depletion-mode device. At V_GS = 0 the channel is open and I_D equals I_DSS, say 5 mA. Applying reverse gate bias reduces current until the pinch-off voltage V_P (for example −3 V) kills it. The square-law model is I_D = I_DSS(1 − V_GS/V_P)² in saturation.

MOSFETs come in both flavours. An enhancement device has no channel at V_GS = 0; it needs V_GS > V_th (say 0.4 V in a 65 nm logic transistor) to invert the surface. A depletion MOSFET has an implanted channel and behaves like a JFET but with an insulated gate, so it can be driven either positive or negative. Digital CMOS relies almost entirely on enhancement devices because "off at zero input" makes a gate with no static current path possible.

Watching pinch-off happen

The animation below shows an n-channel JFET as V_GS sweeps negative. The depletion regions (orange) grow from the gate, the conductive channel narrows, and the electrons streaming from source to drain thin out until the current is choked.

Noise: where the JFET still wins

Thermal noise in the channel is similar for both: roughly 4kTγ/g_m referred to the input, with γ near 2/3 in long-channel saturation and higher in short-channel devices. The real divergence is flicker (1/f) noise. MOSFET carriers move in a thin surface inversion layer and are repeatedly trapped and released by oxide interface states, so 1/f corners reach 10 kHz to several MHz in scaled CMOS. JFET current flows in the bulk, away from the interface, so a part like the LSK389 or 2SK170 achieves around 1–2 nV/√Hz with a very low 1/f corner. That is why JFETs sit at the front of microphone preamps, electrometers, hydrophones and photodiode transimpedance amplifiers.

In IC design you counter MOSFET flicker noise by making the device bigger, since noise power scales roughly as 1/(W·L·C_ox), using PMOS inputs (often quieter), or applying chopping and correlated double sampling. Spectre and HSPICE noise analyses with the foundry 1/f model (KF/AF in older SPICE, or the BSIM noise parameters) let you plot input-referred noise before tape-out.

Key fact: A MOSFET's 1/f noise scales inversely with gate area, so low-noise analog input pairs are often 100 µm × 1 µm or larger, despite the area cost.

Side-by-side summary

Compare this with the bipolar side of the story in our BJT vs MOSFET comparison, and see how source-follower input stages are biased in the common-drain amplifier guide.

Choosing in practice

• Femtoamp-level sensing or ultra-low-noise audio: discrete JFET front end, then follow with an op-amp.
• Switching and power: MOSFET, because enhancement mode gives a safe default-off state.
• Sample-and-hold analog switches: JFET switches are simple and offer low charge injection, but integrated designs use transmission-gate MOSFETs.
• Anything on a chip: MOSFET, since a JFET needs a separate junction process step.

If you want to build this intuition on real SPICE and layout work, the team at Avecas design services uses the same Cadence Virtuoso/Spectre flows we teach, and ChipXpert's training programs cover analog layout hands-on.

Ready to go beyond theory? Explore the analog design tracks in the CourseTron courses and practise device-level simulation on real examples.

FAQ

Can a JFET be used as an enhancement device?

Not in the usual sense. A silicon JFET conducts at V_GS = 0, and forward biasing the gate past roughly 0.5 V turns on the junction, so it behaves as a depletion-only device.

Why is MOSFET input impedance higher than JFET?

The oxide blocks DC current entirely, while a reverse-biased junction has a small leakage current that grows with temperature.

Which has lower noise?

For low-frequency applications the JFET, thanks to bulk conduction and low 1/f noise. At RF both are comparable, and MOSFETs usually win because of higher f_T.

What is pinch-off voltage?

It is the gate-source voltage at which the depletion regions meet and the channel is fully closed, giving near-zero drain current.