In short: A dynamic (StrongARM) comparator uses a clock to trigger positive-feedback regeneration, giving you a rail-to-rail decision with zero static current — but you pay for that in kickback noise and clock-dependent input offset that you must manage carefully, especially inside a SAR ADC.
Why dynamic comparators exist
Every ADC eventually has to answer one binary question billions of times per second: is this voltage above or below that one? A continuous-time amplifier-based comparator can do it, but it burns a fixed bias current the whole time, whether it is deciding or idle. In a modern SAR ADC running at tens of MS/s, that static power is unacceptable. The dynamic comparator solves this elegantly: it only draws current during the brief instant it is making a decision, and settles to zero afterwards. For a 10-bit SAR at 50 MS/s, a well-designed StrongARM comparator can resolve a decision in roughly 150–300 ps while averaging under 50 µW.
The canonical topology is the StrongARM latch (also called the Lewis–Gray or sense-amplifier comparator), which dates back to a 1990s Stanford/ISSCC lineage and now dominates SAR, pipeline, and SerDes receiver front-ends.
How the clocked regeneration works
The StrongARM has three phases driven by a single clock, CLK:
- Reset (CLK low): the tail transistor is off, and reset switches pull both output nodes (and the two internal drain nodes) up to VDD. No current flows. The latch is "armed."
- Sampling / integration (CLK rises): the tail turns on. The differential input pair (M1/M2) discharges the internal nodes at rates set by their gate voltages. The input with the higher voltage discharges its branch faster, converting the input difference into a growing voltage imbalance — this is the input-dependent part.
- Regeneration (latch engages): once the nodes drop enough to turn on the cross-coupled inverter pair, positive feedback takes over. The small imbalance is amplified exponentially until one output slams to VDD and the other to ground.
⚡ Regeneration is exponential: the output difference grows as ΔV·et/τ, where τ = C/gm. Halving the load capacitance or doubling transconductance roughly halves the decision time — the single most important lever for speed.
Kickback noise: the price of switching
Because the internal nodes swing by hundreds of millivolts during regeneration, those transitions couple back through the gate–drain capacitance of the input pair onto the input terminals. This is kickback noise. In a SAR ADC it is especially nasty: the comparator inputs connect directly to the capacitive DAC, so kickback disturbs the very voltage being measured, and the disturbance is data-dependent, producing nonlinearity rather than benign random noise.
Standard mitigations include adding cascode or neutralization devices between the input pair and the regenerating nodes, inserting a pre-amplifier stage (a "two-stage" dynamic comparator) to isolate the inputs, and sizing the input devices to trade gain against Cgd. Designers verify kickback in Cadence Spectre transient simulations by probing the charge injected into a realistic DAC model across input codes.
Offset and how to calibrate it
A dynamic comparator has no static operating point, so its offset is dominated by random mismatch in the input pair and, crucially, by mismatch in the regenerating devices and the reset timing. Unlike an op-amp, you cannot simply trim a bias — the offset is set at the clock edge. For a given technology, input-referred offset σ typically lands in the 5–15 mV range before calibration, far larger than the sub-millivolt LSB of a 12-bit converter.
| Offset source | Scales with | Typical fix |
|---|---|---|
| Input-pair VTH mismatch | 1/√(WL) | Enlarge input devices |
| Load / latch mismatch | Node capacitance ratio | Add calibration caps at output nodes |
| Clock skew to the pair | Layout asymmetry | Common-centroid, matched routing |
? Mismatch improves only as 1/√(area). Cutting offset in half means quadrupling input-device area — which raises kickback and input capacitance. That three-way tension between offset, speed, and kickback is the heart of dynamic-comparator design.
Production SAR ADCs almost always add a digitally controlled offset-calibration array: a bank of small switchable capacitors on the two output nodes, tuned once at startup (or in background) to null the offset to below an LSB. Monte-Carlo mismatch runs in Cadence Spectre or Synopsys HSPICE, plus Siemens (Mentor) Analog FastSPICE for the full SAR loop, are the standard verification flow.
Inside a SAR ADC
In a SAR, the comparator is the only active block, so its noise and metastability set the resolution ceiling. Two subtleties matter. First, thermal noise integrated at the input sets the smallest resolvable signal; designers budget comparator noise at roughly a quarter to a half LSB. Second, metastability: when the input difference is nearly zero, regeneration can take arbitrarily long, and if it hasn't resolved by the next SAR cycle the bit is wrong. You allocate enough regeneration time and sometimes add metastability detection to flag suspect conversions.
For deeper treatment of the trade-offs between continuous-time and clocked topologies, see our companion piece on general comparator design, and the dedicated walkthrough of SAR ADC architecture. If you want hands-on layout and mismatch-characterization practice on a real PDK, our analog design courses run the full Spectre + calibration flow. Teams needing a custom data-converter block built and verified can look at the design-services track at Avecas analog design services.
Design checklist
- Size the input pair for an offset target, then budget area against kickback and input C.
- Add neutralization/cascode or a pre-amp if kickback corrupts the DAC settling.
- Run Monte-Carlo mismatch for offset and delay; both have distributions.
- Allocate regeneration time with metastability margin for the worst near-zero input.
- Include a trim/calibration cap bank for anything above ~10-bit resolution.
Ready to design your own StrongARM latch? Our CourseTron Analog IC track takes you from hand analysis to a calibrated, Monte-Carlo-verified comparator in a real PDK. Explore the analog courses →
Frequently asked questions
Why is it called a "StrongARM" comparator?
The name comes from the DEC StrongARM microprocessor's sense amplifier, whose latch topology was adapted as a standalone clocked comparator. It is also called a sense-amplifier-based or Lewis–Gray comparator.
Does a dynamic comparator really use zero static power?
Essentially yes — it draws current only during the brief decision phase and leakage otherwise. This is why it dominates power-sensitive SAR and SerDes front-ends over continuous-time comparators.
What limits the resolution I can get from a dynamic comparator?
Input-referred thermal noise and residual offset after calibration. Beyond roughly 12 bits you need a low-noise pre-amplifier stage and background offset/noise calibration.
How do I simulate kickback?
Run a transient simulation in Cadence Spectre (or Siemens AFS) with a realistic capacitive-DAC load and sweep input codes, then measure the charge injected back onto the input node per decision — kickback that varies with code is what hurts ADC linearity.