In short: A counter-type (digital-ramp) ADC drives a DAC from a free-running binary counter, stepping its output up one LSB at a time until a comparator detects the DAC has just crossed the analog input — the counter value at that instant is the digital code, so conversion time grows linearly with the input amplitude.
The counter-type ADC — also called the digital-ramp or staircase ADC — is one of the first converter architectures every analog or mixed-signal engineer meets, and for good reason. It contains almost nothing: a comparator, an N-bit binary counter, a DAC, a clock, and a little control logic. Yet it exposes the single idea behind an entire family of feedback converters: generate a known analog quantity, compare it to the unknown input, and adjust until the two agree. Understanding exactly how its counter and DAC "walk up" to the input voltage makes the cleverer architectures — successive-approximation, tracking, and sigma-delta — far easier to reason about.
The core idea: a staircase chasing the input
The converter works by brute-force search. A counter starts at zero and increments on every clock edge. Its output feeds a digital-to-analog converter, so the DAC produces a rising staircase voltage VDAC that climbs one least-significant-bit (LSB) step per clock. A comparator continuously checks VDAC against the sampled analog input Vin. As long as VDAC < Vin, the comparator output stays high and the counter keeps counting. The instant VDAC rises just above Vin, the comparator flips low, the control logic freezes the counter, and the latched counter value is the output code.
Think of it as a feedback loop that searches: the DAC is the actuator, the comparator is the sensor, and the counter is the integrator that remembers how far it has climbed.
A concrete numerical example
Take an 8-bit converter with a 5.12 V reference. One LSB is 5.12 V / 256 = 20 mV. Suppose Vin = 2.00 V. The counter must climb to code 100 (since 100 × 20 mV = 2.00 V) before VDAC crosses the input. At a 1 MHz clock (1 µs per step), that conversion takes 100 µs. Now feed in 4.50 V: the counter must reach code 225, needing 225 µs. Same converter, same clock — more than double the conversion time, purely because the input is larger.
Why conversion time depends on the signal level
This is the architecture's defining limitation and its most interview-relevant trait. Because the staircase always restarts from zero and climbs one step at a time, the number of clock cycles equals the output code itself. A near-zero input converts in a handful of cycles; a full-scale input needs the full 2N − 1 cycles.
| Input (8-bit, 20 mV LSB) | Output code | Clocks @1 MHz | Conversion time |
|---|---|---|---|
| 0.10 V | 5 | 5 | 5 µs |
| 2.00 V | 100 | 100 | 100 µs |
| 5.10 V (near FS) | 255 | 255 | 255 µs |
Engineers must therefore specify the worst-case conversion time, 2N − 1 clock cycles, when setting the sample rate. For a 10-bit converter that is 1023 cycles per sample — which is why a contrasting architecture like the SAR ADC, which needs only N cycles, dominates medium-speed data acquisition.
Control logic and the end-of-conversion flag
Practically, a Start-of-Conversion (SOC) pulse resets the counter to zero and enables counting. The comparator output gates the counter's clock through an AND gate. When the comparator trips, the counter is disabled and an End-of-Conversion (EOC) flag goes high, telling downstream logic (a microcontroller, FPGA, or DMA engine) the code is ready to be latched. In HDL-based designs this is a tiny finite-state machine you could simulate in Synopsys VCS or Siemens Questa in minutes, and the DAC + comparator behavioral models drop straight into a Cadence Virtuoso AMS testbench for mixed-signal verification.
The comparator sets the accuracy floor. Its offset and hysteresis directly add to the converter's effective offset and can cost an LSB or more — which is why real designs chop or auto-zero the comparator, exactly the kind of circuit technique covered in our ADC comparator design guide.
Strengths, weaknesses, and where it still appears
The counter-type ADC's appeal is simplicity and monotonicity: it uses a single comparator (cheap), and its transfer characteristic is inherently monotonic because the DAC output only ever steps upward during a conversion. Its weaknesses are speed and variable latency. The variable, amplitude-dependent conversion time makes it awkward for uniformly sampled systems and essentially unusable for high-bandwidth signals.
A small but important refinement is the tracking (up/down counter) ADC: instead of resetting to zero each time, it uses an up/down counter that increments when VDAC < Vin and decrements otherwise, so once locked it follows a slowly changing input within ±1 LSB per clock. That eliminates the restart penalty for continuous signals at the cost of slew-rate limiting on fast transients. You still see counter-based conversion today in slope/integrating ADCs inside precision digital voltmeters and in simple on-chip housekeeping ADCs where a few hundred microseconds of latency is irrelevant.
If you are building custom silicon around these blocks, firms such as Avecas VLSI design services implement and verify exactly this class of mixed-signal IP on nodes from 180 nm down to advanced FinFET processes.
Want to go from block diagram to a verified RTL + DAC testbench? Our CourseTron Analog & Mixed-Signal track walks you through building a counter-type ADC, a SAR, and a sigma-delta converter hands-on in industry tools.
Frequently asked questions
Why is the counter-type ADC also called a digital-ramp ADC?
Because the counter produces a linearly increasing digital value, the DAC generates a ramp-like (staircase) analog voltage. "Digital-ramp" describes that rising DAC output that ramps up toward the input.
How does its speed compare to a SAR ADC?
A SAR ADC resolves N bits in exactly N clock cycles using binary search, while a counter-type ADC needs up to 2N − 1 cycles. For 10 bits that is roughly 1023 cycles versus 10 — about 100× slower in the worst case.
Is the counter-type ADC monotonic?
Yes. During each conversion the DAC output only steps upward, and conversion stops at the first crossing, so the output code increases monotonically with input voltage, assuming the internal DAC itself is monotonic.
What limits the resolution of this architecture?
The internal DAC's resolution and linearity, the comparator's offset and noise, and clock jitter. Adding bits doubles worst-case conversion time per extra bit, so resolution is traded directly against throughput.