In short: A common-mode feedback (CMFB) loop senses the average of a fully-differential amplifier's two outputs, compares it to a reference, and drives a common bias node so the output common-mode voltage is set precisely — and because it forms its own loop, it must be compensated for stability just like the main differential path.
Every seasoned analog designer has watched a beautiful fully-differential op-amp simulate perfectly open-loop, then rail both outputs to the supply the moment it is dropped into a real testbench. The culprit is almost always a missing or badly tuned common-mode feedback network. This article explains why fully-differential stages cannot survive without CMFB, how to set the output common mode, and how to keep the extra loop from oscillating.
Why a differential amplifier needs CMFB at all
In a single-ended op-amp, the output DC operating point is self-regulating: global negative feedback around the inverting input forces the output to whatever voltage satisfies the loop. A fully-differential amplifier has two outputs, Vop and Von, and the external feedback network only controls the difference Vop − Von. The average, Vocm = (Vop + Von)/2, is left completely unconstrained.
Consider a telescopic cascode with both outputs biased by nominally identical PMOS current sources. If those sources deliver even 1% more current than the NMOS tail can sink, the only way to balance charge is for both output nodes to drift upward until the PMOS devices leave saturation. The differential gain is still huge, but the whole stage has walked off to the rail. CMFB is the dedicated loop that pins Vocm to a chosen reference (commonly VDD/2) while leaving the differential signal untouched.
A fully-differential two-stage amp with 60 dB differential gain can easily have 40–60 dB of common-mode gain to the output nodes as well. Without CMFB the common-mode operating point is set by device mismatch of a few millivolts amplified by that gain — i.e. it is not set at all.
Sensing the common mode
The first job of any CMFB circuit is to extract (Vop + Von)/2 without loading or disturbing the differential signal. Three sensing styles dominate practical designs:
- Resistive divider: two equal resistors from each output to a summing node. Simple and perfectly linear, but the resistors load the output and cost gain. Buffer them or use large values (hundreds of kΩ) in low-power designs.
- Switched-capacitor sensing: capacitors sample and average the outputs on a clock phase. Draws essentially zero static current and is the default in discrete-time sigma-delta and pipeline ADC amplifiers, where a clock already exists.
- Source-coupled / triode MOS sensor: a pair of transistors whose combined current tracks the average output. Compact and continuous-time, but nonlinear for large common-mode swings.
| Sensing method | Static current | Linearity | Typical use |
|---|---|---|---|
| Resistive divider | Finite (loads output) | Excellent | Continuous-time, high-swing |
| Switched-capacitor | Near zero | Excellent | Discrete-time ADC/filter stages |
| MOS triode pair | Low | Moderate | Compact low-power RF/IF |
Whichever you pick, the sensed value feeds an error amplifier that compares it against Vcm,ref and produces a correction current or voltage. That correction almost always steers a tail or load bias so that both outputs move together — the loop has gain only for the common mode and ideally none for the differential mode.
Setting the output common mode precisely
The accuracy of Vocm equals the accuracy of Vcm,ref divided by the CMFB loop gain, plus the error-amp input offset. A loop gain of 40 dB (×100) and a 5 mV reference error leaves roughly 50 µV of common-mode error contributed by the reference path — negligible. Offset in the error amp, however, appears directly, so designers size its input pair generously and sometimes auto-zero it in switched-capacitor implementations.
A concrete example: a 1.8 V analog supply with Vcm,ref = 0.9 V gives each cascode output roughly 450 mV of headroom up and down. Choosing Vocm too high starves the PMOS loads of VDS; too low starves the NMOS. The common mode is therefore a headroom allocation decision, not merely a bias detail. You can see how this interacts with device sizing in our differential pair design guide, and with tail-current budgeting in the cascode current mirror walkthrough.
Stability: the second loop you must compensate
Here is the mistake that bites most newcomers: the CMFB network is a feedback loop in its own right, with its own loop gain, its own poles, and its own phase margin. If you only compensate the differential path, the common-mode loop can ring or oscillate — sometimes visible as a stubborn few-hundred-MHz tone on both outputs that vanishes in differential measurement.
The common-mode loop usually shares the amplifier's output pole, then adds the pole of the error amplifier and any pole from the sensing network. Because the common-mode path often has a different dominant pole location than the differential path, you generally need a separate compensation capacitor in the CMFB loop. In switched-capacitor CMFB, the sampling action itself sets the loop bandwidth, which is one reason that topology is so popular — stability becomes a matter of settling within the clock phase.
Rule of thumb: target the CMFB loop's unity-gain bandwidth at or below the differential loop's, and verify at least 60° of phase margin in a dedicated CM loop-gain simulation — never assume the differential compensation covers it.
Verifying CMFB in simulation
In Cadence Spectre or Synopsys HSPICE/CustomSim you break the common-mode loop with an ideal common-mode probe — inject a test source into the CM path and measure CM loop gain and phase using a stability (STB) or AC analysis, exactly as you would for the differential loop. Siemens (Mentor) Analog FastSPICE is popular for the large mixed-signal blocks where this loop lives. Always run the check across corners: the CMFB error amp's bias and the sensing resistors drift, and a loop that is stable at TT 27 °C can lose phase margin at SS 85 °C. Teams that design these amplifiers for production do exactly this corner-and-Monte-Carlo verification — the kind of silicon-grade analog methodology offered by Avecas design services.
Want to build and compensate a fully-differential op-amp from scratch — schematic, CMFB loop, and layout? The Analog IC Design track on CourseTron courses walks you through every node with real Cadence testbenches.
Frequently asked questions
Does CMFB affect the differential gain?
Ideally no. A well-designed CMFB loop has gain only for the common mode and presents negligible loading to the differential signal. In practice the sensing network (e.g. resistive dividers) does slightly load the outputs, reducing differential gain by a small, predictable amount you budget for up front.
Can I set the output common mode with just well-matched current sources?
No. Matching sets the nominal operating point, but process and temperature mismatch of a few millivolts, amplified by the stage's high common-mode gain, still pushes the outputs toward a rail. CMFB provides the active correction that matching alone cannot.
Why does my fully-differential amp oscillate only in common mode?
Because the CMFB network is a separate feedback loop with its own phase margin. If you compensated only the differential path, the common-mode loop can be under-damped. Run a dedicated common-mode loop-gain (STB) simulation and add compensation to that loop specifically.
Is switched-capacitor CMFB better than continuous-time?
It draws near-zero static current and auto-zeros offset, which is ideal in clocked ADC and filter stages. Continuous-time CMFB is preferred when no clock is available or when the amplifier must settle without clock-phase constraints, such as in RF or wideband signal paths.