Charge pumps in PLLs

In short: A PLL charge pump converts the phase-frequency detector's UP/DOWN pulses into a precise correction current onto the loop filter, and its three dominant non-idealities — UP/DOWN current mismatch, the dead zone, and leakage/charge-sharing — are exactly what set the loop's reference spur level and in-band phase noise floor.

The charge pump (CP) is the quiet workhorse of every classic charge-pump PLL. It sits between the phase-frequency detector (PFD) and the loop filter, and it is where an abstract "phase error" becomes a real analog current slewing a capacitor. Get the charge pump right and the loop is clean; get it wrong and you spend weeks chasing reference spurs on a spectrum analyzer that no amount of divider tweaking will fix. If you are new to the loop itself, start with our PLL design basics primer and come back here for the current-source details.

What the charge pump actually does

The PFD produces two logic outputs, UP and DOWN. When the reference edge leads the feedback (divided VCO) edge, UP goes high for a time proportional to the phase error; when it lags, DOWN goes high. The charge pump translates these into current: an UP pulse switches a current source I_up that pushes charge onto the loop filter, raising the VCO control voltage; a DOWN pulse switches a sink I_dn that pulls charge off. In lock, the loop drives the net charge per reference cycle to zero, so the control voltage holds steady.

The charge-pump gain, often written K_CP = I_CP/2π amperes per radian, is one of the three terms (with the VCO gain K_VCO and the divide ratio N) that set the loop bandwidth. A typical integrated CP runs 100 µA to 2.5 mA; higher I_CP widens the loop and lowers thermal-noise contribution but costs area and headroom.

UP/DOWN current matching

In an ideal CP, I_up = I_dn exactly, at every control voltage. Reality is a PMOS mirror sourcing UP current and an NMOS mirror sinking DOWN current, and these two branches have different output impedances and respond differently to V_ctrl. The result is a current mismatch, typically specified as a percentage, ΔI/I. A 5% mismatch is ordinary for a plain cascode CP; sub-1% needs active feedback (an op-amp forcing the dummy branch to track V_ctrl) or gain-boosted cascodes.

Why it matters: in lock the PFD issues a small simultaneous UP and DOWN pulse every reference cycle (the anti-dead-zone pulse, below). If the two currents are unequal, that pair injects a net charge each cycle. The loop compensates with a static phase offset so the timing imbalance cancels the current imbalance — but the periodic charge glitch at the reference rate modulates V_ctrl, and that FM on the VCO shows up as a reference spur at ±f_ref from the carrier.

The dead zone and why we fight it

If the PFD reset path were perfect, a tiny phase error would produce a pulse too short to fully switch the current sources on — the CP would deliver almost no charge for small errors. That flat region in the gain curve is the dead zone: near lock the loop has essentially zero gain, so the VCO is free to wander within it, producing a noise hump and jitter. The fix is deliberate: add delay in the PFD reset path so both UP and DOWN fire for a minimum overlap (often 0.5–2 ns) every cycle, keeping the current switches fully turned on and the gain linear through zero.

Killing the dead zone and matching the currents pull in opposite directions: a longer anti-dead-zone pulse guarantees linearity but gives any residual mismatch more time to inject charge, raising spurs. Picking that overlap is a classic analog trade-off tuned in simulation.

Leakage and charge sharing

Between pulses the loop capacitor must hold its voltage. Any DC leakage — reverse-biased junction leakage in the switches, gate leakage in deep-submicron VCO varactors, or board-level leakage across a dirty PCB in a discrete design — drains charge continuously. The PFD responds with a steady corrective pulse each cycle, and that periodic pulse is again a reference spur. Leakage-induced spurs grow with temperature (junction leakage roughly doubles every ~10 °C) and are a prime suspect when a board that was clean on the bench degrades in a hot enclosure.

A second effect is charge sharing: the switch drain nodes have parasitic capacitance that, at the instant of switching, dumps or steals a small fixed charge from the output. Because it is independent of phase error, it behaves like a fixed offset and mismatch, again feeding the spur. Careful switch sizing, dummy switches for charge-injection cancellation, and keeping the current-source nodes at the same potential as the output (the "constant V_DS" architecture) all attack this.

Reference spurs: the figure that gets reviewed

Reference spurs are the single most-scrutinised CP spec because they are visible on a spectrum analyzer and directly corrupt adjacent-channel performance in a radio. They are the sum of all the effects above modulating V_ctrl at f_ref. The spur power relative to the carrier scales with the net charge error per cycle, the VCO gain, and inversely with how well the loop filter attenuates at f_ref.

In practice you verify all of this before tape-out with transistor-level simulation: Cadence Spectre (or Spectre X for faster PSS) running a periodic steady-state plus pnoise analysis to read spur level and in-band noise directly, Synopsys HSPICE/CustomCompiler for the CP cell characterisation, and Siemens Eldo/AFS in mixed-signal flows. A PSS run at the reference frequency with the measured current mismatch is the fastest way to predict the spur before you ever touch silicon. Teams doing full analog sign-off, like the engineers at Avecas VLSI design services, fold CP characterisation into the block-level verification plan rather than discovering spurs at the system bring-up.

Practical sizing example

Suppose a 2.4 GHz synthesizer with f_ref = 40 MHz, N = 60, I_CP = 1 mA, K_VCO = 30 MHz/V, targeting a 200 kHz loop bandwidth. If the UP/DOWN mismatch is 3% and the anti-dead-zone overlap is 1 ns, the net charge injected per cycle is roughly 3% × 1 mA × 1 ns = 30 fC. That tiny packet, filtered by the loop and multiplied by K_VCO, lands you a reference spur in the −60 to −70 dBc range — often right at the edge of a spec. Halving the mismatch to 1.5% buys you about 6 dB of spur, which is exactly why the replica-bias CP exists. These are the back-of-envelope numbers interviewers love to walk through.

For a broader tour of synthesizer architecture — integer-N vs fractional-N, loop filter order, and how the divider interacts with the CP — see our companion piece on fractional-N synthesizer design, and browse the full analog track on our courses page.

Want to design and simulate a charge-pump PLL end-to-end in Cadence? The CourseTron Analog & RF IC track walks you from PFD timing to spur budgeting with real Spectre labs — explore the curriculum.

Frequently asked questions

Why does UP/DOWN current mismatch cause a reference spur but not a frequency error?

The loop still locks to the correct average frequency; it simply settles at a small static phase offset so the mismatched currents net to zero charge on average. The problem is that the cancellation happens cycle-by-cycle through a brief charge glitch at f_ref, and that periodic disturbance frequency-modulates the VCO, appearing as a spur offset by the reference frequency.

Can I just remove the anti-dead-zone pulse to reduce spurs?

No. Removing it reintroduces the dead zone, where the loop has near-zero gain around lock and the VCO phase wanders freely, raising close-in phase noise and jitter. The right move is to keep a minimal overlap pulse and instead reduce the current mismatch and leakage that the pulse exposes.

How is leakage different from current mismatch as a spur source?

Mismatch injects charge only during the brief overlap pulse and scales with that pulse width; leakage drains charge continuously between pulses and forces a correction every cycle regardless of pulse width. Leakage is also strongly temperature-dependent, so a leakage-dominated spur grows as the part heats up, whereas a mismatch spur is comparatively stable.

What simulation confirms charge-pump spur performance?

A periodic steady-state (PSS) analysis at the reference period in Cadence Spectre, with the extracted CP current mismatch and leakage applied, reads the spur level directly; a following pnoise analysis gives the in-band phase noise contribution. Synopsys HSPICE and Siemens AFS offer equivalent shooting/harmonic-balance engines for the same characterisation.