In short: The Gajski-Kuhn Y-chart organizes every VLSI design representation onto three radial axes — behavioural, structural and physical — crossed by concentric abstraction levels, so that "design" becomes the act of spiralling inward from a system spec to a fabricated layout.
Ask any VLSI interviewer to name the single mental model that frames the entire chip design process, and the honest answer is the Gajski-Kuhn Y-chart. First published by Daniel Gajski and Robert Kuhn in 1983, it is not a flow diagram you execute step by step — it is a coordinate system for design information. Understanding it is the difference between seeing synthesis, place-and-route and simulation as unrelated tool invocations versus seeing them as movements across one well-defined space.
The three domains: behaviour, structure, physical
The "Y" is three axes radiating from a common centre. Each axis is a domain — a distinct way of describing the same design:
- Behavioural — what the design does, with no commitment to how. A Boolean equation, a C algorithm, a Verilog
alwaysblock describing a FIR filter's transfer function, or a differential equation for an op-amp all live here. - Structural — how it is built from interconnected components. A netlist of gates, flip-flops and wires; a register-ALU-mux datapath; or a block diagram of CPU, cache and bus. Structure says nothing about position on silicon.
- Physical (geometric) — where everything sits. Transistor polygons, standard-cell rows, floorplan rectangles, and the final GDSII mask data that the foundry consumes.
Key fact: The same component appears once on each axis. A 32-bit adder is a behavioural expression (s = a + b), a structural netlist of full-adders, and a physical arrangement of cells — three views of one object, not three objects.
The concentric abstraction levels
Crossing the three axes are four to five concentric circles — the abstraction levels. The outermost ring is the most abstract (system/architecture); the innermost is the most detailed (transistor/polygon). Each level has a meaning on all three axes simultaneously:
| Level | Behavioural | Structural | Physical |
|---|---|---|---|
| System | Executable spec, C/SystemC | Processors, memories, buses | Chips, boards, floorplan |
| Algorithm | Dataflow, FSM | Hardware blocks, modules | Macro-cell clusters |
| RTL | Register transfers | ALUs, registers, MUXes | Macro / module placement |
| Logic | Boolean equations | Gates, flip-flops (netlist) | Standard-cell rows |
| Circuit | Transfer functions, V-I | Transistors, R, C | Polygons, GDSII mask |
Design as a spiral inward
Here is the payoff. A design task is a vector on the chart: it either converts one domain into another at the same level (synthesis) or refines one domain to a lower level (optimization). The entire modern RTL-to-GDS flow traces a counter-clockwise spiral from the outer behavioural axis toward the physical centre.
s=a+b into a gate netlist.Mapping real tools onto these vectors makes the chart concrete:
- Logic synthesis (Synopsys Design Compiler / Fusion Compiler, Cadence Genus) — behavioural RTL → structural gate netlist, staying at the logic level.
- Place and route (Cadence Innovus, Synopsys IC Compiler II) — structural netlist → physical layout, moving toward the centre.
- Logic/RTL simulation (Siemens Questa, Synopsys VCS) — exercises the behavioural axis to verify intent before any structure is committed.
- Physical/LVS verification (Siemens Calibre) — checks that the physical polygons still match the structural netlist, i.e. the two inner axes agree.
Key fact: High-level synthesis (Siemens Catapult, Cadence Stratus) is a longer vector — it jumps from an algorithmic behavioural description straight to an RTL structural netlist, skipping the hand-written RTL step entirely.
Why it still matters at 3 nm
The Y-chart predates FinFETs, but it is more relevant than ever precisely because EDA tools have multiplied. A 2026 tapeout might involve 40+ distinct tools; without a map, an engineer cannot reason about which representation each tool consumes and emits. The chart also explains common bugs: a mismatch between simulation (behavioural) and gate-level results (structural) means your synthesis vector was lossy — usually a non-synthesizable construct or a missing constraint. For the full practical journey, see our walkthrough of the VLSI design flow from RTL to GDS, and the deeper treatment in abstraction levels in digital design.
Teams doing real tapeouts, like the design-services engineers at Avecas VLSI design services, lean on this mental model to hand off cleanly between front-end (behavioural/structural) and back-end (physical) stages.
Want to walk the full Y-chart spiral hands-on — writing the RTL, running synthesis, and pushing to GDS on real tools? Explore CourseTron's VLSI track on our courses page.
FAQ
Who created the Y-chart and when?
Daniel D. Gajski and Robert H. Kuhn introduced it in a 1983 IEEE Computer article on silicon-compilation methodology; it is therefore often called the Gajski-Kuhn chart.
Is the Y-chart a design flow I follow step by step?
No. It is a representation space, not a procedure. Real flows draw paths across it (synthesis, P&R), but the chart itself only tells you which domain and abstraction level any artifact occupies.
What is the difference between the structural and physical domains?
Structural describes components and their connectivity (a netlist) with no geometry; physical adds position, size and shape on the die (placement, routing, polygons). LVS verification exists to confirm the two still agree.
Where does high-level synthesis fit?
It is a behavioural-to-structural transformation at a higher abstraction level — turning an untimed C/SystemC algorithm into timed RTL, a longer inward jump than ordinary logic synthesis.