In short: A stick diagram is a colour-coded, scale-free sketch that captures a CMOS circuit's layout topology — which layers connect to which — so you can plan diffusion runs, Euler paths and routing before committing to a full-scale mask layout.
Every physical IC layout starts life as an abstraction. Before an engineer draws a single rectangle in a tool like Cadence Virtuoso or Synopsys Custom Compiler, they usually sketch a stick diagram: a shorthand that shows where transistors sit, how their source/drain diffusions share a single strip of silicon, and which metal and poly wires knit them together. It is the bridge between a transistor-level schematic and a design-rule-correct layout.
Why stick diagrams exist
A real layout is governed by dozens of design rules — minimum widths, spacings, enclosures, all expressed in nanometres and tied to the process technology (say, a 45 nm or 7 nm node). Worrying about those exact dimensions while you are still deciding the topology of a gate is a distraction. A stick diagram deliberately throws dimensions away and keeps only the connectivity and relative placement. That lets you answer the questions that actually drive layout area: Can the pull-up and pull-down networks share diffusion so there are no breaks? Which signals cross, and will they need a jump to another layer? How wide, in tracks, will the cell be?
A stick diagram is not to scale. A 2 µm poly line and a 45 nm poly line look identical on the sketch. The payoff is topological clarity; the penalty is that you still owe the tool a real, rule-clean layout afterwards.
The colour code
The power of the method is its visual language. Each mask layer gets a fixed colour, so a glance tells you the layer of every wire. The conventions below are the ones taught in most university courses (Weste & Harris) and used in industry sketches:
| Layer | Conventional colour | Represents |
|---|---|---|
| n-diffusion (active) | Green | NMOS source/drain regions |
| p-diffusion (active) | Yellow / brown | PMOS source/drain regions |
| Polysilicon | Red | Transistor gates & short local wires |
| Metal 1 | Blue | Signal / power routing |
| Metal 2 | Purple / grey | Second routing layer |
| Contact / Via | Black dot / X | Layer-to-layer connection |
The single most important rule follows from physics: wherever a red poly line crosses a green or yellow diffusion strip, a transistor is formed at that crossing. Poly over n-diffusion is an NMOS device; poly over p-diffusion is a PMOS device. A contact (black) ties two layers together — for example, metal1 down to diffusion to make a source connection to VSS.
From schematic to layout, one gate at a time
Take the inverter above. The schematic is trivial — one PMOS, one NMOS, gates tied to input A, drains tied to output Y. The stick diagram adds the spatial decision: run a continuous p-diffusion at the top and a continuous n-diffusion at the bottom, drop a single vertical poly stripe for A that gates both, contact the PMOS source to VDD and the NMOS source to VSS, and join the two drains with metal to form Y. Because the two devices share nothing but the gate signal, there is no diffusion break — the cell is as narrow as the design rules allow.
The same discipline scales to compound gates. For a two-input NAND, the two NMOS transistors are in series, so their diffusion must be continuous — the drain of one is the source of the next, no contact between them. The two PMOS devices are in parallel and share both their source and drain nodes. Getting those shared-diffusion decisions right on the stick diagram is exactly what minimises the number of expensive diffusion breaks in the final cell.
Euler paths: the trick that minimises area
When a gate has more than a couple of transistors, the order in which you place them along the diffusion strip decides how many breaks you need. A diffusion break costs area (you must leave spacing and often re-contact), so the goal is a single uninterrupted strip for the pull-up network and another for the pull-down network, with the poly columns in the same left-to-right order for both. That shared gate ordering is what lets a standard cell align its inputs.
The classic result: a break-free layout exists when you can find an Euler path — a walk that traverses every edge exactly once — through both the pull-up and pull-down graphs using the same sequence of gate signals. Model each transistor as an edge labelled by its gate input; the nodes are the circuit nets.
Consider the AOI (AND-OR-INVERT) function Y = (A·B + C·D)'. Build the pull-down graph (series-parallel of the NMOS) and the pull-up graph (the dual). If you find an Euler trail A-B-C-D that is valid in both graphs, you lay the four poly gates down in exactly that order and both diffusion strips run unbroken underneath. If no common Euler path exists, you accept one break — or re-letter the inputs. Tools such as Cadence's automated place-and-route and standard-cell generators solve this combinatorially, but hand-sketching it builds the intuition every layout engineer needs.
Where stick diagrams fit in the modern flow
You might ask whether this is still relevant at 7 nm, where almost all logic is synthesised and placed automatically. The answer is yes, in two places. First, the standard-cell library that every synthesis flow depends on is hand-crafted, and its authors reason in exactly this stick-diagram language — diffusion sharing, gate ordering, track height. Second, analog and custom blocks (bandgaps, SerDes, SRAM bitcells) are still laid out by hand, and the stick sketch is the first artefact an engineer produces. Even verification tools like Siemens Calibre (DRC/LVS) are checking a layout whose topology was first reasoned about this way.
A good exercise is to take a gate, sketch its stick diagram with a correct Euler ordering, then build the real cell in a layout editor and run LVS to prove it matches the schematic. That round trip — schematic → stick → layout → verify — is the core skill. For a deeper treatment of the full physical flow, see our guide to VLSI layout design, and for the geometric constraints that turn a stick sketch into silicon, our walkthrough of CMOS design rules and lambda scaling.
Engineers who master this hands-on intuition tend to interview far better for physical-design roles. If you want structured, project-based training on the full RTL-to-GDSII path, our sister brand Avecas VLSI design services works on real tapeout flows, and you can explore our own curriculum on the CourseTron courses page.
Ready to build layouts, not just read about them? CourseTron's Physical Design track takes you from stick diagrams through standard-cell creation to a full place-and-route flow on an open PDK — enrol and start your first cell today.
FAQ
What is the difference between a stick diagram and a layout?
A stick diagram shows only connectivity and relative placement with colour-coded layers and no real dimensions. A layout is the scaled, design-rule-correct set of polygons that is actually fabricated and verified with DRC and LVS.
Why is the Euler path important in stick diagrams?
A common Euler path through the pull-up and pull-down networks, using the same gate ordering, guarantees you can draw both diffusion strips without a break. That minimises cell width and avoids extra contacts, directly reducing area.
What do the colours mean in a stick diagram?
Green is n-diffusion, yellow/brown is p-diffusion, red is polysilicon (gates), blue is metal1, purple/grey is metal2, and a black dot is a contact or via. A red poly line crossing a diffusion strip forms a transistor at that point.
Are stick diagrams still used in advanced nodes?
Yes. Although digital logic is synthesised automatically, the underlying standard cells and all analog/custom blocks are still hand-designed, and engineers reason about their topology using stick-diagram concepts before committing to geometry.