In short: A modern metal stack is a tiered set of interconnect layers — thin, dense lower metals (Mx) for local wiring, medium intermediate layers (My) for block-level routing, and thick top metals (Mz) for power and global signals — engineered so that wire resistance, capacitance, and electromigration limits are each matched to the job that layer does.
Why a chip needs many metal layers, not one
Transistors live on a single silicon surface, but the wiring that connects billions of them cannot. A high-end SoC at 5 nm carries 14 to 18 metal layers stacked vertically in the back-end-of-line (BEOL), separated by inter-layer dielectric and stitched together by vias. The reason is simple arithmetic: a single routing plane can only hold so many parallel wires before they collide. Stack fifteen planes and you multiply the routing resources, letting a net on layer 3 hop up to layer 9 to fly over a congested region and drop back down near its destination.
But not all layers are built the same, and that is the heart of metal-stack design. The layers closest to the transistors are patterned at the finest pitch the lithography allows — at 5 nm the lowest metal pitch is around 28–30 nm — while the top layers can be 10× to 20× wider and thicker. This tiering is what engineers mean by the Mx / My / Mz convention.
Mx, My, Mz: what each tier does
The three-tier naming is a shorthand foundries use so that the flow does not depend on an exact layer count, which changes between nodes:
- Mx (local / fine) — typically M1 through M3/M4. Minimum pitch, minimum thickness. These carry cell-internal connections and short local nets. Resistance per unit length is very high, so you keep wires short.
- My (intermediate) — a middle band, often M5–M9, patterned at roughly 2× the Mx pitch. This is the workhorse tier for block-level and bus routing.
- Mz (top / thick) — the uppermost layers plus redistribution. Very wide and thick, used for power delivery (PDN), clock spines, and long global signals that must cross the die with low delay.
Key fact: Wire resistance scales as R = ρL / (W·T). Doubling thickness T on a top metal halves its resistance for the same width — which is exactly why power rails live on thick Mz, where IR drop must stay under budget (often <5% of VDD).
Resistance, capacitance and the RC penalty
The lower you go, the thinner and narrower the wire, so resistance rises sharply — a minimum-width M1 wire can exceed hundreds of ohms per micron, while a thick top metal might be a fraction of an ohm per micron. Capacitance behaves differently: closely packed fine wires have high coupling capacitance to their neighbours. The product RC sets interconnect delay, and on long nets this delay can dwarf the gate delay it connects. That is why place-and-route tools such as Synopsys Fusion Compiler and Cadence Innovus promote long, timing-critical nets onto higher layers with lower R, and why non-default routing rules (wider wire, double spacing) are applied to clocks and critical buses.
| Tier | Example layers | Rel. pitch | R per length | Primary use |
|---|---|---|---|---|
| Mx | M1–M4 | 1× | Very high | Cell / local nets |
| My | M5–M9 | ~2× | Medium | Block routing, buses |
| Mz | Top + RDL | 8–20× | Very low | Power, clock, global |
Electromigration and why thick top metal matters
Electromigration (EM) is the gradual displacement of metal atoms by momentum transfer from electrons at high current density. A wire carrying too much current for too long grows voids and eventually opens. The EM limit is expressed as a maximum current density (J), and a wire's current-carrying capacity is proportional to its cross-section W·T. Power and clock nets carry the largest currents, so they are the ones that need the generous cross-sections that only thick Mz layers provide. Sign-off tools like Cadence Voltus and Ansys RedHawk-SC check every segment against its EM and IR limits; a violation on a power strap usually means widening it or moving it to a thicker layer.
Routing resources and congestion
Every layer adds horizontal or vertical routing tracks (layers usually alternate preferred direction). More layers means more tracks, but each via that climbs the stack consumes area and adds resistance. Designers therefore budget layer usage carefully: over-using the thin lower metals creates hotspots the router cannot resolve, a problem we explore in depth in our guide to routing congestion in VLSI. Getting the power delivery network design right on the thick layers is equally critical, because PDN straps steal tracks from signal routing. For teams building real tape-out skills, the hands-on physical-design practice at Avecas VLSI design services complements the theory here.
Key fact: On advanced nodes, foundries also offer "mega" or "ultra-thick" metals above Mz for inductors and RF — these can be 3–4 µm thick, hundreds of times thicker than M1.
Want to master BEOL, parasitics and sign-off hands-on? Explore CourseTron's physical-design track on our courses page and build a real metal-stack-aware floorplan.
FAQ
What is the difference between Mx, My and Mz layers?
They are tiers of increasing pitch and thickness: Mx are the thin, dense local layers near the transistors; My are intermediate layers for block routing; Mz are the thick top layers used for power, clock and global signals.
Why are top metal layers made thick?
Thickness increases cross-sectional area, which lowers resistance (reducing IR drop) and raises electromigration current limits — both essential for power delivery and high-current clock distribution.
How does the metal stack affect timing?
Interconnect delay is set by the RC product. Thin lower layers have high resistance, so long critical nets are promoted to lower-resistance upper layers to cut delay, often with non-default wide/spaced routing rules.
How many metal layers does a modern chip have?
It varies by node and product: advanced SoCs commonly use 14–18 layers, while simpler or older designs may use 6–10.