In short: Global routing plans congestion-aware wiring on a coarse grid of Gcells to assign each net a region and a metal layer, then detailed routing commits those plans to exact tracks, vias and DRC-clean geometry — iterating with rip-up-and-reroute until zero violations remain.
Routing is the last big physical-implementation step before signoff, and it is where a placed-and-optimized netlist finally becomes real metal. Because a modern block can carry millions of nets across 10–15 metal layers, no router solves the whole problem in one pass. Instead, tools such as Cadence Innovus, Synopsys IC Compiler II and the open-source routers split the job into two phases: a fast, approximate global route and an exact, rule-bound detailed route. Understanding the hand-off between them is one of the most common physical-design interview topics, so let us walk through it carefully.
Why routing is split in two
A detailed router must honor hundreds of design rules — minimum spacing, minimum area, via rules, parallel-run-length spacing, end-of-line rules, double-patterning coloring, and antenna limits. Running that machinery on every net from scratch would be hopelessly slow and would get stuck in local congestion traps. So the flow first abstracts the die into a grid of rectangular tiles called Gcells (global-routing cells), each a handful of routing tracks wide. The global router reasons only about which Gcells a net passes through and how many wires can cross each Gcell boundary — the edge capacity.
A Gcell is typically sized at the pitch of a few routing tracks (for example 8–16 tracks per side). If a 7nm Gcell edge offers 10 tracks and the router wants to push 13 nets through it, that edge has an overflow of 3 — the headline number every global route tries to drive to zero.
Phase 1 — Global routing
The global router models the chip as a graph: nodes are Gcells, edges carry a capacity equal to the number of tracks that can legally cross. It then routes every net as a tree through this graph, choosing a corridor and a set of metal layers while trying to keep every edge below capacity. Classic engines use maze or A* search, but modern routers (and research tools like NCTU-GR and the ISPD-contest routers) lean on Rectilinear Steiner Minimal Trees plus negotiation-based congestion pricing: an over-used edge gets a rising cost so that later nets voluntarily detour around the hot spot.
The output is not geometry. It is a routing guide — for each net, the ordered Gcells and preferred layers, plus a congestion map the designer inspects before committing. If global route reports persistent overflow, the right fix is usually upstream (spread the placement, add a layer, resize buffers), not forcing detailed route to perform miracles.
Track assignment — the bridge
Between the two phases sits track assignment. The long, straight segments of each global route (the "trunk" wires) are assigned to specific routing tracks within their Gcells and layers, respecting preferred direction (M2 horizontal, M3 vertical, and so on). Track assignment resolves most of the easy contention cheaply and in bulk, so that the far slower detailed router only has to stitch the short connections, jogs, and vias. Good track assignment can eliminate 80–90% of potential shorts before detailed routing even starts, which is why it is a distinct, timed stage in Innovus and ICC2.
Phase 2 — Detailed routing
Detailed routing takes the guides and track assignments and produces real, manufacturable wires: exact coordinates, layer changes through legal via arrays, and geometry that passes every foundry rule. It works on the full, fine routing grid rather than Gcells, and it is the phase that actually touches the technology LEF/techfile. Here a wrong-way jog, a missing via-enclosure, or an end-of-line spacing miss becomes a hard DRC violation.
On advanced nodes the detailed router must also satisfy coloring for multi-patterning (LELE/SADP). A segment that is DRC-clean in isolation can still fail if it forces an odd cycle in the same-color spacing graph — which is why "DRC-clean" at 7nm means rule-clean and color-legal.
Rip-up and reroute (RRR)
No router lays every net correctly on the first try. When two nets collide, the detailed router does rip-up-and-reroute: it tears out one or more offending segments, raises the cost of the congested area, and reroutes the victims along a cheaper path. This loop repeats over multiple iterations, each one shaving the violation count. A healthy run shows a monotonic decay — for example 42,000 → 6,500 → 900 → 40 → 0 violations across five iterations. If the count plateaus (say it sticks at ~300 for three passes), the block is genuinely congested and you stop burning runtime and go fix placement or layer resources.
Global vs detailed at a glance
| Aspect | Global routing | Detailed routing |
|---|---|---|
| Granularity | Gcells (coarse) | Routing tracks (exact) |
| Goal | Balance congestion, pick layers | DRC-clean real geometry |
| Output | Routing guides + congestion map | Legal wires, vias, coloring |
| Rules checked | Edge capacity only | Full LEF/techfile DRC |
| Runtime share | Small | Large (RRR dominates) |
Where it fits in the flow
Routing follows placement, clock-tree synthesis and pre-route optimization, and feeds signoff timing, parasitic extraction (QRC/StarRC) and physical verification (Calibre/Pegasus). If you want the broader picture, see our overview of routing in VLSI and the companion piece on congestion analysis and fixes. Teams building production flows often pair in-house training with hands-on design support from a dedicated physical-design services group to close real tapeout blocks.
Want to run global and detailed routing on a live block in Innovus and ICC2, read congestion maps, and drive violations to zero yourself? Join the physical-design track on CourseTron courses.
FAQ
Can detailed routing fix a bad global route?
Only partially. If global route reports heavy, persistent overflow, detailed routing will either fail to converge or produce long detours that hurt timing. The fix belongs upstream — spread placement, add a metal layer, or resize cells — before rerunning.
What is the difference between a Gcell and a routing track?
A routing track is a single legal centerline for a wire on one layer. A Gcell is a tile spanning several tracks, used only by the global router to count capacity; detailed routing ignores Gcells and works on the real track grid.
Why does rip-up-and-reroute increase net cost instead of just moving wires?
Negotiation-based routing raises the cost of congested regions each iteration, so nets that have cheaper alternatives voluntarily move away. This lets the router escape the local traps that a simple "move the loser" heuristic gets stuck in.
What does "DRC-clean" mean on a 7nm node specifically?
It means the geometry passes all spacing, enclosure, end-of-line and minimum-area rules and is color-legal for multi-patterning. A shape can be rule-legal yet still fail because it forces an illegal same-color spacing conflict.