In short: Electromigration is the gradual, current-driven displacement of metal atoms in on-chip wires; VLSI signoff uses Black's equation and per-layer current-density (J) limits to prove every power, ground and signal net survives its target lifetime at operating temperature.
If you have ever wondered why a chip that passes timing and DRC can still fail in the field after two years of service, electromigration (EM) is one of the usual suspects. It is a reliability failure mechanism, not a functional bug, which makes it invisible to simulation and brutal in volume production. Below is how practising physical-design and signoff engineers actually reason about it.
The physics: momentum transfer, not heat
Inside a copper or aluminium interconnect, the conduction electrons are not passive. When current density gets high, each electron carries real momentum, and collisions with the metal lattice transfer some of that momentum to the atoms. This "electron wind" nudges metal atoms in the direction of electron flow (opposite to conventional current). Over billions of collisions the atoms drift, leaving voids upstream (an open) and hillocks or extrusions downstream (a short to the neighbour). Both are catastrophic.
The key variable is current density J = I / A (amps per unit cross-sectional area), not current alone. A 1 mA current in a wide power strap is harmless; the same 1 mA squeezed through a single minimum-width via can exceed the limit. This is why EM is fundamentally a geometry-and-current problem that only the physical layout can resolve.
Black's equation: turning physics into a lifetime number
J.R. Black's 1969 empirical model remains the workhorse. It predicts the median time to failure (MTTF):
MTTF = (A / Jⁿ) · exp(Eₐ / kT)
where J is current density, n is the current-density exponent (typically 1–2; ~2 for void-nucleation-limited failure), Eₐ is the activation energy (~0.7–0.9 eV for copper, ~0.5–0.6 eV for aluminium), k is Boltzmann's constant and T is absolute temperature. The A prefactor folds in geometry and process.
Why temperature dominates: because T sits inside an exponential, a junction running at 125 °C instead of 85 °C can cut EM lifetime by more than half for the same current density. EM signoff is always run at the worst-case (highest) operating temperature, and self-heating (Joule heating of the wire itself) is added on top of ambient.
Current-density limits: the numbers foundries actually give you
The foundry's technology file defines, per metal layer and per via, the maximum allowed current for three stress types. You rarely see raw J; the tool consumes limits expressed as current for a given width. Representative figures for an advanced node:
| Stress type | What it stresses | Typical limit basis |
|---|---|---|
| Average (DC) EM | Steady unidirectional current (power/ground) | ~1–2 mA per µm of wire width; Black's equation |
| RMS (self-heating) | Joule heating regardless of direction | Capped so ΔT stays within a few °C |
| Peak / transient | Short current spikes on fast signals | Higher limit, short-duration |
The Blech effect gives you a free pass sometimes: below a critical product of current density and wire length (the "Blech length", J·L threshold), back-stress from accumulated atoms cancels the electron wind and the wire is immortal. Short wires are inherently safer, which is why EM violations cluster on long, narrow, high-current nets.
Signoff flow: power/ground versus signal EM
EM signoff splits into two distinct problems, and tools treat them differently.
- Power/ground (PG) EM carries large unidirectional DC current, so average-EM dominates. It is analysed together with IR drop in a power-integrity tool because the same current map feeds both. Tools: Ansys RedHawk-SC / Totem, Cadence Voltus. A weak PG grid shows up as both excessive IR drop and EM hotspots on the same straps.
- Signal EM carries bidirectional current that largely self-cancels on average, so RMS (self-heating) and peak limits usually bind instead. High-fanout, high-toggle nets and clock trees are the worst offenders. Tools: Cadence Quantus/Voltus, Synopsys StarRC + PrimePower/signal-EM flows, Siemens Calibre PERC for rule-based checks.
How engineers actually fix EM violations
Because the lever is J = I/A, almost every fix either reduces I or increases A:
- Widen the wire (increase A) — the first and most common fix on power straps.
- Add parallel/redundant vias — a single via is the classic bottleneck; doubling via count halves per-via current.
- Add parallel routing / multiple fingers on high-current nets, or promote to an upper, thicker metal layer.
- Reduce drive / split the load — downsizing an over-driven buffer or splitting fanout lowers I.
- Exploit short wires (Blech) — keep high-current segments under the immortal length where the node allows.
Good floorplanning and a robust PG mesh built early prevents most PG-EM problems before placement even finishes. This is exactly the kind of signoff discipline our physical-design signoff coursework drills, and the same current analysis underpins the companion IR-drop flow. Teams that want a production design partner often work with Avecas's silicon design services for tapeout-grade EM/IR closure.
Want to run real EM/IR signoff on an industry-style design database? Our CourseTron VLSI Physical Design program takes you from PG-grid construction to full EM closure on commercial tools.
Frequently asked questions
Is electromigration worse in copper or aluminium?
Copper has a higher activation energy (~0.8 eV vs ~0.5 eV for Al), so bulk copper is more EM-resistant. But in copper, failure shifts to interfaces and barrier/liner layers, so advanced nodes still need careful via and liner engineering.
Why is EM checked at the highest temperature?
Temperature enters Black's equation inside an exponential, so lifetime falls steeply as T rises. Signing off at the worst-case junction temperature, plus wire self-heating, guarantees the margin holds across the whole operating range.
Does lowering the clock frequency help signal EM?
Often yes. Signal EM is usually RMS- and peak-limited; lower toggle rates reduce RMS current and self-heating, easing the limit. Power-ground DC EM, however, depends on average current draw, not frequency alone.
What is the difference between EM and IR drop?
Both stem from the same current map, but IR drop is an instantaneous voltage-loss (functional/timing) problem, while EM is a long-term atomic-wear (reliability/lifetime) problem. A single weak power strap can cause both at once.