In short: Double (redundant) via insertion replaces single vias in the routed netlist with two parallel vias wherever room allows, so a single via void or electromigration failure does not open the net — a near-free reliability and yield win that place-and-route tools apply automatically after detailed routing.
Vias are the quiet weak point of every modern chip. A wire can be re-routed, a cell can be re-placed, but the tiny tungsten or copper plug that connects metal 3 to metal 4 either fills correctly in the fab or it does not. At advanced nodes a surprising fraction of all yield loss and field failures trace back to a single defective via. Double via insertion — sometimes called redundant via insertion (RVI) — is the design-stage answer: wherever a single via sits, drop a second one in parallel so the connection survives even if one via is defective. This article explains why vias fail, how much redundant vias buy you, the DRC and routing constraints involved, and exactly when the EDA tools add them.
Why a single via is a liability
A via is a vertical hole etched between two metal layers and filled with metal. Two independent failure mechanisms make a lone via risky:
- Random manufacturing defects. Partial fill, a particle in the etch, or misalignment can leave a via with high resistance or no connection at all. Via defect density is one of the dominant contributors to random yield loss at 28 nm and below.
- Electromigration (EM). Current crowds at the via-to-metal interface. Over years of operation, metal atoms drift and a void nucleates there, eventually opening the net. The current a single via can carry reliably is capped by EM rules in the technology file.
Put two vias in parallel and both problems improve dramatically. A random defect now has to hit both vias to open the net; if the single-via open probability is p, the double-via open probability is roughly p², which turns a 1-in-1,000 event into a 1-in-a-million event. For EM, two vias split the current, so each carries half and the connection meets its lifetime target with margin.
On a large SoC the router may place tens of millions of vias. Even a defect rate of a few parts-per-million per via becomes a measurable yield hit — which is why foundries publish redundant-via coverage as a sign-off metric and often set a target of 90–99% of eligible vias doubled.
When the tools insert redundant vias
Redundant via insertion is a post-route optimization. It runs after detailed routing, once the exact via locations and surrounding metal are known, and typically before or during final sign-off DRC. The flow is: route the design, then ask the router to walk every via and convert it to a double (or 2x2 array) if the geometry permits. In Cadence Innovus this is driven by commands such as setViaGenMode and the redundant-via options in optDesign -postRoute; in Synopsys IC Compiler II it is a step in route_opt / route_detail with redundant-via settings enabled, and in Siemens Calibre or Nitro-SoC similar rules apply. The physical-verification tool (Calibre, IC Validator, Pegasus) then reports the achieved redundant-via rate.
Crucially, the tool only converts a via when doing so does not create a DRC violation. The decision is local and greedy: can a second cut be placed adjacent to this one, extending the metal enclosure, without shorting to a neighbor or violating spacing? If yes, double it; if not, leave the single via. That is why 100% coverage is almost never achieved on a congested design.
The DRC and geometry constraints
Inserting a second via is not free real estate. Every added cut must still satisfy the full design-rule set of the metal/via layers involved:
| Constraint | What it limits |
|---|---|
| Via-to-via spacing | Minimum gap between the two cuts of the pair |
| Metal enclosure | Each via needs minimum metal overlap on both layers; two vias need a wider pad |
| Adjacent-net spacing | The enlarged metal must not violate spacing to a neighboring wire |
| Min-area / notch rules | The resulting metal shape must still be a legal polygon |
Because the enlarged landing pad needs extra room, redundant vias go in easily in sparse regions and fail to go in inside dense, highly congested channels — precisely where wires are packed tightest. Good physical design therefore reserves a little routing margin so RVI can hit its target; this is one of the many reasons routing quality and via redundancy are tightly linked. See our deeper dive on routing in VLSI and on electromigration sign-off for how these interact.
Single cut, double cut, and via arrays
"Double via" is the common case, but the same idea scales. Wide power straps and high-current nets often use 2×2 or larger via arrays so that both EM capacity and redundancy scale with the current. On power grids the via array is sized to the strap width during floorplanning, not left to the post-route pass. For ordinary signal nets, a simple pair is the default target, and the tool will fall back to a single via only where geometry forbids a second.
A useful rule of thumb: redundant-via insertion typically adds negligible area (vias reuse existing routing tracks) and no timing penalty — a doubled via actually lowers via resistance slightly, which marginally helps delay and IR drop.
Measuring and signing off coverage
Teams track the redundant-via rate = doubled vias ÷ total vias, often split per via layer (V1, V2, … Vtop). A typical sign-off goal is 90%+ overall, with the understanding that the lowest, densest layers (V1) score worst and the upper layers score near 100%. If a block falls short, the usual fixes are: loosen congestion by spreading placement, add an extra RVI pass, or allow the router to legally shift wires to open landing room. Foundries sometimes mandate a minimum coverage for reliability-critical products such as automotive (AEC-Q100) parts.
For a hands-on treatment of these flows with real tool scripts, Avecas's physical design services team works through redundant-via tuning on production tape-outs.
Common pitfalls
- Chasing 100%. The last few percent cost enormous effort for tiny benefit; set a realistic per-layer target.
- Ignoring the power grid. Post-route RVI handles signal vias, but PG via arrays must be sized up front.
- Running RVI before ECOs. Any post-RVI routing change can strand a redundant pair; re-run insertion after the last ECO.
- Mismatched tech data. If the via rules in the technology LEF/ITF don't match the foundry deck, inserted vias may pass the router but fail Calibre DRC.
Want to run Innovus and IC Compiler II redundant-via flows yourself on a real block? CourseTron's physical-design track walks you through routing, RVI, EM/IR and sign-off end to end — explore the VLSI courses.
FAQ
Does double via insertion increase die area?
Almost never in a meaningful way. Redundant vias reuse existing routing tracks and only enlarge local metal pads, so area impact is negligible. The benefit — lower via resistance and far higher reliability — comes essentially for free.
At what stage of the flow does it run?
After detailed routing and before final DRC sign-off. The tool needs the exact routed geometry to know where a second cut will fit, so it is a post-route optimization, re-run after any late ECOs.
Why can't the tool reach 100% coverage?
In congested regions there is no legal room for a second cut without violating via-spacing, metal-enclosure or adjacent-net spacing rules. Those vias stay single. Dense lower layers like V1 score lowest; upper layers approach 100%.
Is redundant via insertion the same as via arrays on power nets?
They share the goal but differ in stage. Signal-net doubling is an automatic post-route pass, while power-grid via arrays are sized during floorplanning to carry strap current and are not left to the RVI step.