Verilog 4 Bit Booth Multiplier

In short: Booth recoding rewrites a signed multiplier as digits from {−1, 0, +1} (radix-2) or {−2, −1, 0, +1, +2} (radix-4), so a 4-bit signed multiply needs only two partial products instead of four, and the whole datapath fits in a small encoder, a select-and-negate stage and one adder.

Why signed multiplication needs a smarter approach

A schoolbook multiplier generates one partial product per multiplier bit and sums them. That works for unsigned numbers, but two's-complement operands break the pattern: the top bit carries negative weight, so the last partial product must be subtracted, and every earlier row needs correct sign extension. Andrew Booth proposed his recoding in 1950 to tame both problems at once, and it is still the front end of most signed multipliers synthesized today, including the DSP blocks you instantiate on FPGAs.

The core observation is arithmetic, not clever hardware: a run of ones such as 0111 equals 1000 − 0001. Instead of adding three shifted copies of the multiplicand, you subtract once and add once. The longer the run of ones, the bigger the saving, and the sign bit stops being special because it simply ends a run.

Radix-2 Booth recoding in one rule

Append a phantom bit q₋₁ = 0 to the right of the multiplier. Then look at each pair (q_i, q_i−1) and pick the digit:

• 00 or 11: digit 0, add nothing (middle of a run).
• 01: digit +1, add the multiplicand (end of a run of ones).
• 10: digit −1, subtract the multiplicand (start of a run of ones).

Take M = 0111 (+7) and Q = 1101 (−3). The pairs, from the top, give digits 0, −1, +1, −1, whose weighted sum is −4 + 2 − 1 = −3, which is exactly the multiplier. The partial products are −7, +14, −28 and 0, and their sum is −21, the correct product, with no special case for the negative operand.

Key fact: radix-2 Booth does not guarantee fewer partial products. An alternating multiplier such as 0101 produces a non-zero digit in every position, so the worst case is no better than a plain array. That is the reason hardware uses radix-4.

Radix-4 (modified Booth): halving the rows

Modified Booth, usually credited to MacSorley, examines overlapping groups of three bits (q_2i+1, q_2i, q_2i−1) and steps two bits at a time. Each group yields one digit in {−2…+2} with weight 4ⁱ, so an n-bit multiplier always produces n/2 partial products, regardless of the data. Multiplying by 2 is just a left shift, and negation is an inversion plus a carry-in, so every digit is cheap to build.

Watching the recoder slide across the multiplier

The animation below walks the three-bit window over Q = 1101 with the phantom zero appended. The window starts at the least significant end, decodes 010 as +1, then jumps two bits left and decodes 110 as −1. Note that the windows share one bit; that overlap is what stitches the runs of ones together.

The datapath: encoder, selector, adder

Hardware for one radix-4 row has three pieces. The encoder turns three multiplier bits into control lines (commonly named one, two, neg). The selector is an AND-OR mux that picks M or M shifted by one, and an XOR with neg performs the inversion. Finally, the neg bit is fed back as a carry-in at the row's least significant position, completing the two's-complement negate without a second adder. For a 4-bit multiplier you get two such rows and one final adder producing the 8-bit product.

A 4-bit Booth multiplier in Verilog

The version below is combinational and synthesizable. It keeps the operands signed so the compiler handles extension correctly; if you are unsure why x = m widens with the sign bit, read our note on Verilog data types and the sign extension rules.

module booth4 (
  input  signed [3:0] a,   // multiplicand
  input  signed [3:0] b,   // multiplier
  output signed [7:0] p    // product
);
  function signed [7:0] pp(input signed [3:0] m, input [2:0] g);
    reg signed [7:0] x;
    begin
      x = m;                       // sign-extends to 8 bits
      case (g)
        3'b000, 3'b111: pp = 8'sd0;
        3'b001, 3'b010: pp = x;
        3'b011:         pp = x << 1;
        3'b100:         pp = -(x << 1);
        default:        pp = -x;   // 101, 110
      endcase
    end
  endfunction

  wire [2:0] g0 = {b[1], b[0], 1'b0};
  wire [2:0] g1 = {b[3], b[2], b[1]};

  assign p = pp(a, g0) + (pp(a, g1) << 2);
endmodule

This behavioural form lets synthesis infer the negate and add. If you want to control the structure, such as hand-placing the carry-in trick, restructure it with gate-level instances as described in structural modeling in Verilog. Check it exhaustively: with only 256 input combinations, a testbench can compare every result against a * b in microseconds.

Key fact: the corner case that catches most students is a = −8 (1000) with group 100, which needs −2M = +16 in a signed 8-bit result. It fits in 8 bits, but only because the function widens before shifting; shifting a 4-bit value first would overflow.

Where Booth helps, and where it does not

In ASIC flows, Synopsys Design Compiler and Cadence Genus both recognise multiplications and pick architectures from the DesignWare or GenusIP libraries, typically a radix-4 Booth encoder feeding a Wallace or Dadda compressor tree. Booth wins on wide operands (16 bits and up), where halving the rows removes a full compressor level. At 4 bits the gain is small: the encoder and selector cost real gates, and a plain array can tie it on area. On FPGAs the question is mostly moot, because the dedicated DSP slices from AMD or Intel already contain hard multipliers, so hand-written Booth logic rarely beats the inferred block. The reasons still matter in interviews: expect questions on digit sets, the worst case of radix-2, and why modified Booth always yields n/2 rows. If you are comparing vendors, our Xilinx vs Intel FPGA comparison covers how each handles DSP inference.

Teams that need production arithmetic blocks often get them designed and verified by a partner such as Avecas design services, and learners can build the same fundamentals through hands-on ChipXpert VLSI training.

Ready to go beyond one multiplier? Explore the hands-on RTL and FPGA tracks in our CourseTron courses and build, simulate and synthesize arithmetic blocks yourself.

Frequently asked questions

Does Booth's algorithm always make multiplication faster?

No. Radix-2 Booth has a worst case of one non-zero digit per bit, so it can be no better than a simple array. Radix-4 guarantees n/2 partial products, but the encoder and selector add delay, so the benefit shows mainly at 16 bits and above.

Why does radix-4 use the digits −2 to +2?

Two multiplier bits can represent four values, and the overlapping third bit carries a borrow from the group below. Together they span −2 to +2, and every one of those multiples is a shift and/or negation of the multiplicand, so no real multiplier is needed to form them.

How wide is the product of an n-bit by n-bit signed multiply?

2n bits. For 4-bit operands the range is −56 to +64 (for example −8 × −8 = 64), which needs 8 bits in two's complement.

Should I write Booth multipliers by hand for an FPGA?

Usually not. Write a * b with signed operands and let the tool map it onto DSP slices. Hand-written Booth logic is mainly for learning, custom-width datapaths, or ASIC work.