FPGA I/O standards

In short: An FPGA I/O standard is the electrical contract (voltage swing, reference, termination, and signaling style) a pin must honor — you pick it per bank to match the external device, respect the bank's single VCCIO rail, and choose single-ended standards like LVCMOS for slow control and differential ones like LVDS or SSTL for fast, noise-tolerant links.

Every signal that crosses the boundary of an FPGA passes through a configurable I/O buffer. Unlike an ASIC pad, that buffer is not frozen in silicon — you select its behavior in your constraints file (a Xilinx XDC, an Intel QSF, or Lattice SDC-like syntax). Choosing the wrong standard is one of the most common reasons a board that passes synthesis still fails on the bench: the logic is correct, but the electrical contract between chips is broken. This article explains how LVCMOS, LVDS, and SSTL work, why banks and VCCIO constrain your choices, and how to pick correctly.

What an I/O standard actually specifies

An I/O standard is a named bundle of electrical parameters. When you write set_property IOSTANDARD LVCMOS18 [get_ports clk_en], you are telling the tool four things at once:

• Logic thresholds — the VIH/VIL input decision levels and the VOH/VOL output levels.
• Reference scheme — whether the receiver compares against a fixed fraction of the rail (single-ended), a differential partner, or an externally supplied VREF.
• Drive and slew — for push-pull standards, how many milliamps the driver sources and how fast it switches.
• Termination expectations — whether the standard assumes on-die termination (ODT / DCI) or external resistors.

? LVCMOS is "rail-to-rail": a logic 1 drives essentially to VCCIO and a 0 to ground. That full swing is why LVCMOS is simple and robust at low speed, but also why it radiates and consumes more dynamic power as frequency climbs.

The three families you must know

LVCMOS (Low-Voltage CMOS) is the workhorse single-ended standard, named by its rail: LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS12. Use it for resets, enables, SPI, I2C, LEDs, and anything below roughly 200 MHz. The receiver simply compares the pin against ~50% of VCCIO.

LVDS (Low-Voltage Differential Signaling, ANSI/TIA/EIA-644) sends a signal as the difference between two pins driven by a ~3.5 mA current source into a 100 Ω load, giving a small ~350 mV swing around a ~1.2 V common mode. Because the receiver looks only at the difference, common-mode noise cancels. LVDS carries gigabit SerDes, LCD and camera links, and high-speed source-synchronous buses while radiating far less than a toggling LVCMOS pin.

SSTL (Stub-Series Terminated Logic) is the memory-interface family — SSTL15 for DDR3, SSTL135 for DDR3L, and the related POD/HSTL variants for DDR4/GDDR. SSTL is single-ended but referenced: each input compares the pin against an externally supplied VREF (typically VCCIO/2) and relies on series + parallel termination to tame the reflections on a multi-drop memory bus.

Banks and the VCCIO rail

FPGA I/O pins are grouped into banks — typically 50 pins on a Xilinx 7-series HR bank, fewer on HP banks. Every pin in a bank shares one VCCIO supply. This is the single most important physical constraint in I/O planning: you cannot mix standards in a bank that demand different VCCIO voltages.

Concretely, LVCMOS33 needs VCCIO = 3.3 V, SSTL15 needs 1.5 V, and LVDS on a high-range bank expects ~2.5 V. Put all three in one bank and the tool throws a DRC error such as Vivado's "conflicting VCCIO" message. The fix is planning: group every 3.3 V peripheral into one bank, your DDR3 pins into a 1.5 V bank, and your SerDes pairs into appropriate HP/GTX banks. Some banks also need a VREF pin (for SSTL/HSTL) and a dedicated clock-capable (CC) pin pair for LVDS clocks.

⚠️ A frequent lab failure: an HP (high-performance) bank on 7-series cannot exceed 1.8 V VCCIO, so LVCMOS33 is simply illegal there. Always check the datasheet's bank type before committing a pinout to the PCB.

Termination: on-die vs external

At high edge rates, an unterminated trace reflects energy back and corrupts the eye. Each family answers this differently:

Modern FPGAs provide Digitally Controlled Impedance (DCI) or On-Die Termination (ODT), letting the silicon synthesize the parallel resistor internally so you remove discrete parts from the board. This is essential for DDR, where dozens of nets would otherwise each need a VTT resistor. You enable it in constraints, e.g. IOSTANDARD SSTL15_DCI.

How to pick the right standard

Work from the device on the other end, not from the FPGA. Ask three questions:

• What does the external chip require? A DDR3 part dictates SSTL15; an image sensor may mandate sub-LVDS; a 3.3 V microcontroller forces LVCMOS33. The FPGA adapts to them.
• How fast and how noisy? Below ~200 MHz single-ended LVCMOS is fine. Above that, or across a noisy backplane, go differential (LVDS) for the noise immunity and lower EMI.
• Can the bank support it? Confirm the VCCIO, VREF, and pin-type (clock-capable, DCI-master) requirements fit your floorplan before routing.

Then verify in simulation. Signal-integrity tools from Siemens (HyperLynx) and Cadence (Sigrity) let you run IBIS-model eye diagrams for your exact stackup, and Synopsys HSPICE is common for pre-silicon buffer characterization. These catch a marginal termination choice long before boards are fabricated. For a deeper treatment of how the timing side interacts with I/O delays, see our companion guide on timing constraints and SDC in FPGA design, and if you are debugging a link that passes functionally but fails on hardware, our note on signal integrity basics for FPGA I/O walks through eye-diagram reading.

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Teams building production boards often pair this knowledge with professional review; firms such as Avecas VLSI design services handle I/O planning and SI sign-off on complex FPGA/ASIC boards when in-house bandwidth is tight.

Frequently Asked Questions

Can I mix LVCMOS33 and SSTL15 in the same FPGA bank?

No. LVCMOS33 needs VCCIO = 3.3 V and SSTL15 needs 1.5 V, and a bank has a single VCCIO rail. They must go in separate banks, or the place-and-route tool will flag a VCCIO conflict DRC error.

Why does SSTL need a VREF pin but LVCMOS does not?

LVCMOS receivers compare against a built-in fraction of VCCIO, so the decision level is implicit. SSTL uses a small-swing signal around VCCIO/2 for speed and power, so it needs an explicit, clean VREF rail for the receiver to decide 1 from 0 reliably.

When should I choose LVDS over LVCMOS?

Use LVDS whenever the link is fast (hundreds of MHz to gigabits), travels across a noisy board or connector, or must keep EMI low. Its differential nature cancels common-mode noise and the small swing radiates far less than full-rail LVCMOS toggling.

What is DCI / ODT and do I always need external resistors?

DCI (Xilinx) and ODT (Intel) are digitally controlled on-die terminations that synthesize the matching resistor inside the FPGA. For DDR interfaces this removes dozens of discrete VTT resistors from the board. You enable it via the _DCI suffix in the IOSTANDARD constraint.