In short: A SRAM-based FPGA forgets its design at power-off, so a bitstream generated from your HDL (or HLS-produced RTL) must be loaded each time, either over JTAG during development or automatically from SPI flash at power-up, depending on the configuration mode pins.
Why an FPGA needs to be "programmed" at all
An FPGA is not running software. Its lookup tables, routing switches and block-RAM contents are bits in SRAM cells, and those bits are the circuit. SRAM is volatile, so every power cycle wipes the design. That single fact explains almost everything about configuration: something external must hold the bitstream and push it in, every time. If you are new to the fabric itself, start with What Is FPGA, then come back here.
Size matters for planning. An Artix-7 XC7A35T needs roughly 17.5 Mbit (about 2.2 MB) of configuration data, while large UltraScale+ parts need hundreds of megabits. Unless you enable bitstream compression, the file size is essentially constant for a given device, regardless of how little logic you used. That surprises many beginners: an empty design is as big as a full one.
From source code to bitstream
The path is a pipeline: synthesis maps your RTL to device primitives, place-and-route fixes each primitive to a physical site and each net to a routing path, timing analysis signs it off, and a bitstream writer serialises the result. Vendor tools such as AMD Vivado and Intel Quartus run this flow; ASIC-oriented tools from Synopsys (Design Compiler, Synplify) and Cadence (Genus) solve a similar synthesis problem for different targets. Our walkthrough of the FPGA bitstream and configuration article covers the file format in more depth.
HDL versus HLS: where each fits
HDL (Verilog, VHDL, SystemVerilog) describes hardware cycle by cycle: you decide registers, clocks and pipeline stages. High-level synthesis starts from C or C++ and lets a tool such as Vitis HLS or Siemens Catapult infer the schedule and pipelining. HLS is excellent for datapaths like FIR filters or image kernels; HDL remains the choice for clock-domain crossings, interfaces and anything timing-critical. Read HLS (High-Level Synthesis) for the trade-offs.
Key fact: HLS does not bypass configuration. It only generates RTL; that RTL still passes through the same synthesis, place-and-route and bitstream stages.
A practical example: a 3x3 convolution written in C++ with a pipeline pragma can reach an initiation interval of 1 (one output per clock), which in hand-written HDL means designing line buffers and a window register array yourself. Interviewers like to ask what the initiation interval means and why loop-carried dependencies raise it; see Pipelining in FPGA to build intuition.
JTAG: the development path
JTAG (IEEE 1149.1) uses four signals: TCK, TMS, TDI and TDO. A 16-state TAP controller, steered by TMS on each rising TCK, selects whether you shift an instruction or data register. To configure, the host loads the vendor's CFG_IN instruction, then shifts the bitstream into TDI. A typical programming cable runs TCK at 6 to 30 MHz, so a 17.5 Mbit bitstream takes roughly one second.
JTAG always works regardless of the mode pins, which is why it is the rescue path when flash is blank or corrupt. The same chain also supports boundary scan for board test and, with debug cores such as Vivado's ILA, logic analysis inside the fabric.
Configuration modes and SPI flash
For a product you cannot attach a laptop. Instead the mode pins M[2:0], sampled when PROG_B is released, select who drives the clock. In Master SPI mode (M[2:0] = 001 on 7-series) the FPGA drives CCLK to an external SPI NOR flash, issues a fast-read command and streams the bitstream back, optionally over four data lines. In slave modes (SelectMAP, serial) an external processor or CPLD pushes the data instead.
| Mode | Who drives the clock | Typical use |
|---|---|---|
| JTAG | Host cable (TCK) | Debug, first bring-up, flash programming |
| Master SPI (x1/x2/x4) | FPGA (CCLK) | Standalone boards, low pin count |
| Master BPI (parallel NOR) | FPGA | Fast boot, large bitstreams |
| Slave SelectMAP / Serial | External MCU or CPLD | Processor-managed, partial reconfiguration |
The power-up sequence, in motion
After power rails settle, the FPGA clears its configuration memory (INIT_B goes high when clearing is done), samples the mode pins, loads the bitstream while checking a CRC, then runs a start-up sequence and raises DONE. If the CRC fails, INIT_B is pulled low and the device stays unconfigured. A scope on DONE is the first debugging step on a board that "does nothing".
Key fact: Loading the bitstream over JTAG into SRAM is temporary. To make it permanent you program the SPI flash (often via JTAG and a bridge design), then the FPGA self-loads next boot.
Reliability, security and alternatives
- Radiation: a cosmic-ray bit flip in configuration SRAM changes the circuit; read SEU and mitigation in FPGA for scrubbing and TMR.
- Security: modern bitstreams are AES-256 encrypted and authenticated (RSA or ECDSA) so flash contents cannot be cloned or tampered with.
- Boot time: x4 SPI at 66 MHz loads 17.5 Mbit in roughly 70 ms; compression and multiboot (fallback images) improve speed and field-update safety.
- Non-volatile families: flash or antifuse devices (Microchip PolarFire, Lattice MachXO) keep configuration on-chip and boot instantly.
For comparisons with fixed-function silicon, see FPGA vs ASIC and FPGA vs Microcontroller, where "programming" means something entirely different. To practise the bring-up of real boards under mentorship, explore hands-on programmes at ChipXpert training.
Want to go from blinking an LED to building a complete boot-from-flash design? Join the FPGA track in our CourseTron courses and build it yourself.
Frequently asked questions
Why does my FPGA lose its design when I unplug the board?
Because configuration lives in volatile SRAM. Loading via JTAG is temporary; write the bitstream to SPI flash to make it boot automatically.
Is JTAG or SPI flash faster?
Master SPI at x4 and tens of MHz is usually faster than a JTAG cable, which is limited by cable clock rates. JTAG is still preferred for development because it needs no flash image.
Does HLS replace Verilog or VHDL?
No. HLS generates RTL that goes through the same flow. It speeds up datapath design, while HDL stays essential for interfaces, clocking and control.
What does the DONE pin tell me?
DONE goes high after a successful load and start-up. If it stays low with INIT_B low, the CRC failed or the flash read was bad.