FPGA Block Diagram Explained

In short: An FPGA is a sea of programmable logic blocks (CLBs) stitched together by a hierarchical routing network, ringed by I/O blocks and punctuated by columns of block RAM and DSP slices, with a dedicated clock network feeding every one of them.

Ask ten engineers to sketch an FPGA and you will get ten different drawings. Interviewers love this question because the drawing reveals whether you understand the device or have only used it. This article walks through the standard block diagram, explains why each block exists, and shows how a single signal travels through all of them. If you are new to the device itself, start with our primer on what an FPGA is.

The big picture: an array, not a netlist

A modern FPGA, such as an AMD/Xilinx UltraScale+ or an Intel Agilex part, is not a pile of gates. It is a regular two-dimensional array of tiles. Most tiles are logic, but at fixed columns the vendor inserts hard blocks that would be wasteful to build from logic: memory, multipliers, transceivers and clock managers. The regularity is deliberate. A repeating pattern is easy to manufacture, easy to fit with software, and lets one bitstream format describe millions of cells.

CLBs: where your logic actually lives

A configurable logic block holds the LUTs and flip-flops that implement everything from a state machine to a CRC. In an UltraScale+ device one CLB contains eight 6-input LUTs and sixteen flip-flops, plus carry logic and wide multiplexers. A LUT6 is just a 64-bit SRAM addressed by its six inputs, so it can realise any Boolean function of six variables; the bitstream simply writes the truth table into it.

Key fact: A 4-bit adder built from generic LUTs and routing is slow. The dedicated carry chain moves the carry between adjacent slices on a hard wire, which is why synthesis maps adders and comparators onto it automatically.

Routing: the part that decides your timing

Here is the number that surprises newcomers: in most FPGAs, routing consumes the majority of silicon area and a large share of path delay, often well over half of a typical critical path. Logic delay through a LUT is a few hundred picoseconds; a long net can cost more than that in wire and switch delay alone.

The routing is hierarchical. Each logic tile has a switch matrix made of programmable multiplexers controlled by configuration SRAM bits. Short wires connect neighbouring tiles, mid-length wires span a few tiles, and long lines cross a large part of the die. The router in Vivado or Quartus picks a combination to meet timing. This is also why the same RTL can close timing in one placement and fail in another: the placer decided how far apart two connected blocks end up.

• Short hops: cheapest, ideal for tightly coupled logic.
• Long lines: fewer switches in series, good for high-fanout control signals.
• Dedicated paths: carry chains, cascade buses between DSPs and BRAMs, and clock wires skip the general fabric entirely.

Block RAM and DSP slices: hard blocks for hard problems

Building a 36 Kb memory from LUT RAM would burn hundreds of LUTs and wreck timing. Instead the vendor drops hard SRAM columns into the fabric. A Xilinx RAMB36 stores 36 Kb, is true dual-port, and can be split into two independent 18 Kb halves. Details on ports, write modes and ECC are in our guide to Block RAM (BRAM) in an FPGA.

Likewise, a multiplier-accumulator is awful in LUTs but cheap as hard silicon. The DSP48E2 slice contains a 27x18 signed multiplier, a pre-adder and a 48-bit accumulator, and runs at 600+ MHz when its internal pipeline registers are used. A 128-tap FIR filter maps to 128 slices chained through dedicated cascade wires with almost no fabric routing. See the DSP slice (DSP48) in an FPGA for the full structure.

IOBs: the boundary with the real world

I/O blocks sit in banks around the die edge. Each bank has one supply voltage (VCCO), so a single bank can drive LVCMOS18 or SSTL15 but not both. Inside the IOB you find input and output buffers, programmable drive strength and termination (DCI), plus serializer/deserializer logic used for DDR memory and LVDS links. Pin planning is a design task in its own right: banks, clock-capable pins and simultaneous-switching-noise limits all constrain where signals can go.

Clocking: the network that never goes through the fabric

Clocks travel on dedicated low-skew trees, never ordinary routing. A clock management tile (MMCM or PLL) multiplies, divides and phase-shifts an input clock; global clock buffers then drive it to every flip-flop in a region. The result is skew of tens of picoseconds across the die. Read more in our guides to FPGA clocking and, for crossing between domains, metastability in FPGAs.

Key fact: Never gate a clock with LUT logic. Use a clock-enable on the flip-flops or a clock buffer primitive; a LUT-generated clock lands on general routing and breaks timing analysis.

One signal, end to end

Follow a sample from an ADC pin to a DAC pin. The pad enters an IOB, the routing carries it to CLB logic that conditions it, a BRAM buffers a block of samples, a DSP slice applies a filter, and an IOB drives it out. The animation below shows the path with the clock running underneath.

In practice you would pipeline each stage so one sample enters every clock while earlier samples are still in flight; our article on pipelining in FPGAs explains how to do it without breaking latency budgets. Tools such as Vivado, Quartus, and Synopsys Synplify map your RTL onto exactly these resources, and the utilisation report tells you how many of each block you consumed.

Common interview traps

• "Is an FPGA just gates?" No. Memory, DSP, I/O and clocking are hard blocks, which is why FPGAs reach speeds that a pure LUT array could not.
• "Why did timing fail after a small change?" Placement moved connected blocks apart; routing delay dominates.
• "LUT RAM or BRAM?" Use LUT RAM for small, shallow memories (under roughly 64 words); use BRAM beyond that.

Want hands-on practice with floorplanning, constraints and timing closure? Our team at ChipXpert runs instructor-led VLSI and FPGA training, and you can browse our structured CourseTron courses to build the skills step by step.

FAQ

What are the main blocks in an FPGA?

Configurable logic blocks, programmable routing, I/O blocks, block RAM, DSP slices and clock management tiles, all configured by a bitstream stored in SRAM.

Why is routing so important in an FPGA?

Routing takes most of the die area and a large part of path delay. Poor placement lengthens wires and is the usual reason timing closure fails.

What is the difference between BRAM and distributed RAM?

BRAM is a dedicated hard memory block of 18 or 36 Kb. Distributed RAM reuses LUTs as small memories, which suits shallow, fast storage but consumes logic.

Can I use any pin for a clock input?

No. Use clock-capable pins that connect to the global clock buffers; ordinary pins reach clocks only through general routing, which adds skew.

Ready to go beyond diagrams? Enrol in the CourseTron FPGA course and practise placing, routing and closing timing on real designs.