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PIC Microcontroller Basics

By CourseTron Team ·  7 min read ·  Updated Oct 2026 💬 𝕏 in f
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    In short: A PIC is a Harvard-architecture RISC microcontroller from Microchip with separate program and data buses, a single working register and a 4-clock instruction cycle, and its PIC16 (14-bit instructions) and PIC18 (16-bit instructions) families trade raw speed per clock against AVR for rich, cheap, rugged peripherals.

    Why PIC still matters

    The PIC line traces back to General Instrument's PIC1650 in the 1970s and now ships from Microchip in the billions every year. Walk into any product teardown, from a washing-machine board to a motor-control drive, and there is a decent chance a small PIC is quietly doing the housekeeping. Interviewers like it because it is a compact, honest example of how architecture choices ripple into code size, timing determinism and cost. If you can explain why a PIC behaves the way it does, you understand the basics of every 8-bit core. This guide builds on our deeper walkthrough in PIC microcontroller architecture.

    Harvard RISC: the core idea

    A von Neumann machine fetches instructions and data over one shared bus, so a load or store stalls the next fetch. A Harvard machine keeps program memory and data memory physically separate, each with its own address and data bus. The PIC goes further: the program bus width is chosen to match the instruction. PIC16 uses a 14-bit-wide flash word, so an opcode and its operand (a literal or a 7-bit file address) arrive in one fetch. That is why a PIC16 has only 35 instructions yet needs no multi-byte decoding.

    Von Neumann (one bus) vs Harvard (two buses) Von Neumann CPU Unified memory code + data 1 bus Fetch and load/store take turns. Harvard (PIC) CPU Program flash 14-bit words Data RAM / SFR 8-bit bytes Fetch and data access overlap in the same cycle. CourseTron · coursetron.com
    Separate buses let a PIC fetch the next opcode while the current one reads or writes RAM.

    Key fact: One PIC instruction cycle is 4 oscillator clocks (Q1 to Q4). At a 20 MHz clock that is 5 MIPS, and because fetch overlaps execute, most instructions finish in one cycle; only branches, calls and skips that are taken cost two.

    The register model: WREG and the file registers

    Classic PICs are accumulator-style. Almost every ALU operation involves the working register, WREG, and one "file register" (any RAM or special-function address). The destination bit d chooses whether the result lands in WREG or back in the file register, so ADDWF count,F increments memory in place with no load or store pair. PIC16 data memory is banked: a 7-bit address reaches only 128 bytes, so the BSR/RP bits select the bank. Forgetting to switch banks before touching a peripheral register is the most common beginner bug and a favourite interview question.

            BANKSEL TRISB      ; select bank holding TRISB
            CLRF    TRISB      ; all of PORTB = outputs
            BANKSEL PORTB
            MOVLW   0x55
            MOVWF   PORTB      ; drive alternate pins high

    The call stack is a hardware stack separate from data RAM: 8 levels on PIC16 mid-range, 31 on PIC18. It cannot be read or indexed, so deep recursion is simply not an option, and compilers like Microchip's XC8 build a static call graph to overlay local variables instead.

    PIC12, PIC16, PIC18: choosing a family

    Microchip numbers its 8-bit cores by instruction width. The baseline PIC10/12 uses 12-bit words, mid-range PIC16 uses 14-bit words, and PIC18 uses 16-bit words with a 21-bit program counter that can address 2 MB of flash.

    FeaturePIC16 (mid-range)PIC18
    Instruction width14-bit16-bit
    Instruction count35about 75 (83 with extended set)
    Hardware stack8 levels31 levels
    Hardware multiplierNone on most8x8 single-cycle
    Max program memoryTypically 2K to 28K wordsUp to 2 MB
    InterruptsOne vectorHigh and low priority
    Typical top speed20 MHz (5 MIPS)64 MHz (16 MIPS)

    Rule of thumb: pick PIC16 for sensor nodes, appliance control and anything cost-driven. Move to PIC18 when you need a C-friendly stack, priority interrupts, USB or CAN. Newer "Q" parts blur the line with core-independent peripherals, but the interview-level distinctions above still hold.

    Fetch and execute overlap (animated) FETCH read flash word EXECUTE ALU + write result Result Orange = instruction N, blue = instruction N+1. While N executes, N+1 is already being fetched, so throughput is one instruction per 4-clock cycle. A taken branch flushes the fetched word: 2 cycles. CourseTron · coursetron.com
    The two-stage pipeline: two instructions are in flight at once, one fetching and one executing.

    Peripherals: where PIC earns its keep

    The CPU is modest; the peripheral set is the selling point. A typical mid-range part integrates:

    • 10-bit ADC (12-bit on many newer parts) with up to 28 channels, so a thermistor or pot reads without external converters.
    • 8- and 16-bit timers, plus CCP/ECCP modules that capture, compare or generate PWM. The enhanced module adds half-bridge and full-bridge drive with dead-band insertion for motors.
    • EUSART, SPI and I2C in the MSSP block, plus USB, CAN or LIN on larger PIC18s.
    • Analogue comparators, a fixed voltage reference, and a watchdog timer with its own on-chip RC oscillator.
    • Brown-out reset, power-on reset and 25 mA per-pin drive, enough to light an LED directly.

    That last point matters in the field: a PIC pin can source or sink 25 mA, and the part tolerates 5 V supplies with sloppy decoupling. This ruggedness is why industrial designers keep choosing it.

    Key fact: Port writes on classic PICs are read-modify-write, so back-to-back bit operations on one port can corrupt a pin whose output has not yet settled. Use the LATx register for writes and PORTx only for reads.

    PIC versus AVR versus 8051

    All three are 8-bit and all three are Harvard in the strict sense of separate code and data spaces. The differences lie in the execution model.

    Clocks per basic instruction (typical) Classic 8051 12 clocks per machine cycle PIC16 / PIC18 4 clocks AVR 1 clock Fewer clocks per instruction does not mean a better chip; compare MIPS per mA and peripherals. CourseTron · coursetron.com
    Bar length is proportional to clocks per instruction: 8051 at 12, PIC at 4, AVR at 1.
    • AVR has 32 general registers, executes most instructions in one clock, and was designed with C compilers in mind. At 16 MHz it delivers close to 16 MIPS, which is why Arduino boards chose it.
    • PIC needs 4 clocks, so a 16 MHz PIC gives 4 MIPS. It claws back value with richer analogue peripherals, wider voltage range and lower cost at the very bottom end (6-pin parts).
    • 8051 is accumulator-based with bit-addressable RAM, excellent for Boolean control, and survives mainly as an IP core inside SoCs and in cheap legacy designs. Original timing is 12 clocks per cycle, though modern clones run at 1 or 4.

    For a quick feel of how such cores are verified before tape-out, see our AVR versus ARM Cortex-M comparison. If you are interested in taking an embedded core into silicon, the physical design side is covered by the training team at ChipXpert VLSI training.

    Practical tips for your first PIC project

    • Use MPLAB X with the XC8 compiler and the MPLAB Code Configurator to generate peripheral setup; hand-write only what you must.
    • Always set configuration bits (oscillator, watchdog, brown-out). A wrong oscillator setting gives you a dead chip that looks broken but is not.
    • Disable the analogue function on pins you want digital: on many parts the ANSEL register defaults to analogue and reads pins as 0.
    • Keep interrupt handlers short, and clear the flag bit before returning or you will re-enter forever.

    Our CourseTron embedded courses walk through each of these with timing diagrams and lab exercises.

    Ready to go beyond blinking LEDs? Join the CourseTron Embedded Systems course and build real PIC, AVR and ARM projects with guided labs.

    Frequently asked questions

    Is a PIC a RISC processor?

    Yes, in spirit. It has a small fixed-width instruction set, a load/store-like register file and single-cycle execution for most instructions. It is not a pure load/store design, since instructions operate directly on memory.

    Why does a PIC need 4 clocks per instruction?

    The core divides each instruction into four quadrature phases (Q1 to Q4) that drive decode, read, execute and write inside one cycle. Pipelining hides fetch time, so the 4-clock cost buys simple, small logic.

    Should I learn PIC16 or PIC18 first?

    Start with PIC16 to understand banking, WREG and the hardware stack, then move to PIC18, which is far friendlier to C and gives you priority interrupts and a multiplier.

    Is PIC better than AVR?

    Neither wins universally. AVR gives more speed per clock and cleaner C; PIC gives broader peripheral choice, tougher I/O and very low-cost small packages.

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