In short: On the ESP32-S3, GPIO19/20 are the native USB pins, GPIO26-37 are consumed by flash and PSRAM depending on module variant, GPIO0/3/45/46 are strapping pins that set boot behaviour at reset, and the dual-core LX7 adds 128-bit SIMD vector instructions that speed up neural-network kernels.
Why the S3 pinout is not a free-for-all
The ESP32-S3 has 45 physical GPIOs (GPIO0-21 and GPIO26-48), yet a typical dev board lets you use fewer than 35 of them. The rest are claimed by the memory interface, the USB PHY or the boot logic. Anyone who has stared at a board that boots fine on the bench but hangs when a sensor is wired to the "wrong" pin has met this problem. If you are coming from the older chip, read our ESP32 pin diagram guide first; the S3 changes several assumptions made there.
The key idea is that the GPIO matrix routes most peripherals to any pad, but a handful of functions are hard-wired in silicon: the USB D+/D-, the SPI flash lines, and the strapping latches. Those cannot be remapped, so they define your real design budget.
USB OTG on GPIO19 and GPIO20
The S3 integrates a full-speed (12 Mbit/s) USB 2.0 OTG controller and PHY. The differential pair is fixed: GPIO19 is D- and GPIO20 is D+. The same pads also serve the built-in USB Serial/JTAG controller, which is why many S3 boards can be flashed and debugged over one cable with no external UART bridge.
- Device mode: the chip enumerates as CDC serial, HID, MSC or a custom class using TinyUSB in ESP-IDF.
- Host mode: OTG lets the S3 read a USB stick or keyboard, provided you supply 5 V VBUS yourself and respect its current limit.
- Layout: route D+/D- as a 90 ohm differential pair, keep stubs short, and add ESD protection with low capacitance (below ~3 pF) so signal eye margin survives.
Key fact: because GPIO19/20 are the USB pair, using them as ordinary GPIO disables native USB. After reset they default to the USB Serial/JTAG function, so a pin you thought was idle can still be driven by the PHY.
Octal PSRAM and the reserved pins
The S3 can address external PSRAM through the same SPI controller as flash. With quad-SPI parts, the lines live on GPIO26-32 (the flash and quad PSRAM share CLK, with separate chip selects, CS0 on GPIO29 and CS1 on GPIO26). Modules marked with an "R8" suffix, such as the ESP32-S3-WROOM-1 N8R8, use octal (8-bit wide) PSRAM. That consumes extra data lines plus the data strobe, which is why GPIO33-37 become unavailable as well.
The throughput motivation is simple arithmetic: an 80 MHz octal DDR link moves 8 bits on both clock edges, roughly 160 MB/s peak, versus about 40 MB/s for quad at the same clock. That headroom matters for camera frame buffers and LVGL display buffers.
| Module variant | Flash | PSRAM | Pins lost |
|---|---|---|---|
| N8 (8 MB flash) | Quad | None | GPIO26-32 |
| N8R2 | Quad | Quad 2 MB | GPIO26-32 |
| N8R8 | Quad | Octal 8 MB | GPIO26-32, 33-37 |
| N16R8 / octal flash parts | Quad or octal | Octal | GPIO26-37 |
Key fact: GPIO26-32 are almost never exposed on module castellations, and GPIO33-37 are physically routed out on some boards but must stay unconnected on octal-PSRAM variants. Always check the exact module datasheet, not the bare chip.
Strapping pins: four bits decide your boot
Strapping pins are sampled by the chip only during the reset release window, via the internal latch. After that they revert to normal GPIO. Misusing them is the number-one cause of "works after pressing the button, fails on cold power-up" bugs.
- GPIO0: internal pull-up. High at reset = boot from SPI flash; low = serial download mode. The BOOT button on dev boards simply grounds it.
- GPIO3: selects the JTAG signal source (pad JTAG versus USB Serial/JTAG). Floating by default, so leave it alone unless you know the eFuse setting.
- GPIO45: sets the VDD_SPI flash supply voltage, 3.3 V when low and 1.8 V when high at reset (when not overridden by eFuse). Pulling it up on a 3.3 V flash module can brown out the flash.
- GPIO46: together with GPIO0 chooses the download-boot type, and also influences whether the ROM prints boot messages. It has an internal pull-down.
The practical rule: never hang a strong external pull-up or load, a relay driver or an LED to ground on these four pins unless the idle level matches the default. Strapping behaviour is also an early example of what physical-design teams verify in power-on-reset analysis; see our deeper material on reset logic in the ESP32 boot process walkthrough.
AI vector instructions on the LX7 cores
The S3 pairs two Xtensa LX7 cores (up to 240 MHz) with custom instruction extensions for 128-bit SIMD. A single vector operation can process sixteen 8-bit, eight 16-bit or four 32-bit elements, and fused multiply-accumulate forms cover the inner loops of convolution and fully connected layers. Espressif's ESP-NN and ESP-DL libraries use them, and TensorFlow Lite Micro kernels can be redirected there.
Take an int8 dot product of length 64. The scalar core issues 64 multiply-accumulates; with 16 lanes per instruction the same work needs about 4 vector MACs plus loads. Measured gains on convolution layers are typically several times, not the full 16, because loads, requantisation and memory latency dominate. That is why PSRAM bandwidth, discussed above, and AI speed are linked: weights streaming from PSRAM can starve the vector unit.
Key fact: the vector extension is internal to the cores, so it needs no pin at all, but it still depends on pin decisions through which memory (internal SRAM or octal PSRAM) feeds it.
A pin-budget checklist before you route the board
- Pick the module first (N8, N8R8, N16R8), then freeze which of GPIO26-37 are gone.
- Reserve GPIO19/20 for USB, or accept losing native USB and JTAG.
- Keep GPIO0, 3, 45 and 46 at their default idle levels at reset; use buffers if a peripheral could drive them.
- For ESP-IDF, keep
menuconfigPSRAM mode (quad/octal) in sync with the hardware, otherwise boot fails with a PSRAM init error.
Design-services teams such as Avecas run the same checklist when taking custom S3 boards to production, and our CourseTron embedded courses practise it on real hardware. For the memory-mapped side, see the ESP32 memory map explained.
Ready to design your own ESP32-S3 board with confidence? Explore the embedded track in our CourseTron courses and build a USB device, camera pipeline and TinyML demo step by step.
FAQ
Which ESP32-S3 pins are used for USB?
GPIO19 is D- and GPIO20 is D+. They serve both the USB OTG controller and the USB Serial/JTAG block.
Which GPIOs can I not use with octal PSRAM?
GPIO26-32 are used by flash and PSRAM, and GPIO33-37 are additionally reserved on octal PSRAM or octal flash variants such as N8R8.
What are the ESP32-S3 strapping pins?
GPIO0, GPIO3, GPIO45 and GPIO46. They are sampled at reset to choose boot mode, JTAG source and flash voltage.
Does the ESP32-S3 really accelerate AI?
Yes. Its 128-bit SIMD instructions speed up int8 and int16 neural-network kernels, usually several times versus scalar code, although memory bandwidth limits the full gain.