In short: The 8051's Program Status Word (PSW) is an 8-bit SFR at address 0xD0 that holds the arithmetic result flags (Carry, Auxiliary Carry, Overflow, Parity) and the two register-bank-select bits (RS1, RS0) that pick one of four banks of R0–R7 in internal RAM.
If you have ever single-stepped an 8051 program in Keil µVision and watched a conditional jump go the "wrong" way, the answer almost always lives in one byte: the Program Status Word. The PSW is the 8051's condition-code register. Every arithmetic and logical instruction quietly updates it, and instructions such as JC, JNC, JB PSW.2 and the bank-switched register accesses read it back. Understanding each bit is the difference between guessing and knowing why your code branches the way it does.
Where the PSW sits in the 8051 architecture
The PSW is one of the 8051's Special Function Registers (SFRs), the memory-mapped control registers that live in the upper 128 bytes of internal data memory. It occupies byte address 0xD0. Because that address is divisible by 8, the PSW is bit-addressable: each of its eight bits can be set, cleared, or tested individually with a single instruction (bit addresses 0xD0 through 0xD7). For the full map of the other control registers around it, see our guide to the 8051 Special Function Registers.
The arithmetic flags: CY, AC, OV and P
Carry (CY, PSW.7)
The Carry flag captures the carry-out of bit 7 during unsigned 8-bit addition, and the borrow during subtraction. Add 0xFF + 0x01 and the result wraps to 0x00 with CY = 1. It is also the destination/source for the rotate-through-carry instructions (RLC A, RRC A) and acts as the "boolean accumulator" for the 8051's bit-processor instructions (SETB C, ANL C,bit). JC and JNC branch on it.
Auxiliary Carry (AC, PSW.6)
AC flags a carry out of bit 3 into bit 4 — the "half-carry". Its one real job is BCD arithmetic: after adding two packed-BCD bytes, the DA A (decimal adjust) instruction inspects AC (and CY) to decide whether to add 0x06 to the low nibble. For example, 0x09 + 0x08 = 0x11 sets AC because bit 3 overflowed; DA A then corrects it to the BCD value 0x17.
Overflow (OV, PSW.2)
OV signals signed two's-complement overflow: the result is wrong when interpreted as a signed −128…+127 value. Hardware computes it as the XOR of the carry into bit 7 and the carry out of bit 7. Classic case: 0x50 + 0x50 = 0xA0. As unsigned that is 160 and CY = 0; as signed it is +80 + +80 = +160, which cannot fit, so OV = 1 and the byte reads as −96.
Key fact: CY and OV answer different questions about the same addition. CY tells you whether the unsigned result overflowed; OV tells you whether the signed result overflowed. A single ADD can set one, both, or neither.
Parity (P, PSW.0)
Unlike the others, P is not latched by one instruction and left alone — it is recomputed continuously by hardware after every cycle to reflect the accumulator. P = 1 whenever the number of 1-bits in A is odd (even parity convention: P makes the total even). It is used for serial-link parity checks. Because it tracks A directly, you cannot usefully write it yourself.
| Flag | Bit | Set when… | Primary use |
|---|---|---|---|
| CY (Carry) | PSW.7 | Carry/borrow out of bit 7 | Unsigned math, multi-byte add, bit engine |
| AC (Aux Carry) | PSW.6 | Carry out of bit 3 | DA A for packed BCD |
| OV (Overflow) | PSW.2 | Signed result out of range | Signed math, MUL/DIV status |
| P (Parity) | PSW.0 | Odd number of 1s in A | Serial parity |
Key fact: MUL AB and DIV AB reuse OV with new meanings — after MUL, OV = 1 means the product exceeded 0xFF (high byte in B is non-zero); after DIV, OV = 1 flags a divide-by-zero. Both always clear CY.
Register bank select: RS1 (PSW.4) and RS0 (PSW.3)
The 8051 gives you four banks of the general registers R0–R7, stacked in the lowest 32 bytes of internal RAM (0x00–0x1F). At any moment only one bank is "live" — the one named Rn in your instructions. RS1:RS0 is a 2-bit selector that chooses which:
00→ Bank 0, RAM0x00–0x07(reset default)01→ Bank 1, RAM0x08–0x0F10→ Bank 2, RAM0x10–0x1711→ Bank 3, RAM0x18–0x1F
This is the 8051's fast context-switch trick. An interrupt service routine can switch to a private bank with MOV PSW,#08H instead of pushing and popping R0–R7 on the stack — a single two-cycle write versus sixteen stack operations. In Keil C51 you express the same intent with using 1 on the ISR declaration. The animation below shows the active-bank pointer sliding as RS1:RS0 counts up.
Key fact: Banks you are not using are still plain RAM. If an ISR claims Bank 1 but your main code also uses indirect addressing or a stack that reaches 0x08–0x0F, you will silently corrupt the ISR's registers — a classic bug hunt in any 8051 interrupt programming project.
User flags and the reserved bit
PSW.5 is F0, a general-purpose user flag you can set, clear and test (JB F0,label) to carry a one-bit status between routines. PSW.1 (sometimes called F1 or UD) is user-definable on the original Intel MCS-51; on many modern derivatives it is reserved, so portable code should not rely on it.
Reading and writing the PSW in practice
Because it is bit-addressable, you rarely touch the whole byte except when switching banks. Tool-chains from Keil and the open-source SDCC both predefine PSW, CY, OV, etc. When you debug a signed-math routine in a simulator — whether µVision, SDCC's sdcdb, or a gate-level netlist signed off in Synopsys or Cadence flows for a soft-core 8051 — the PSW view is where you confirm the flags match your hand calculation.
Teams building custom 8051-compatible cores for FPGA or ASIC (for instance, verification against a golden model in Siemens Questa) treat the PSW as a first-class part of the architectural state that must match the reference model on every instruction retirement. If your organisation is standing up that kind of RTL-to-signoff flow, the design-services team at Avecas VLSI design services works on exactly these soft-core verification problems.
Want to master the 8051 from registers to real firmware? Our hands-on CourseTron Embedded Systems course walks you through the PSW, timers, interrupts and serial I/O with lab exercises on real hardware.
Frequently asked questions
Is the PSW cleared on reset?
Yes. After power-on reset the PSW reads 0x00, meaning all flags are cleared and RS1:RS0 = 00, so Bank 0 is active and the stack pointer starts at 0x07.
Why does the 8051 have both a Carry and an Overflow flag?
They serve unsigned and signed arithmetic respectively. The hardware cannot know whether you intend a byte as 0–255 or −128…+127, so it maintains both: CY for unsigned carry/borrow and OV for signed overflow. Your code checks whichever matches your data type.
Can I write to the Parity bit directly?
You can issue an instruction that writes PSW.0, but the hardware recomputes P from the accumulator every cycle, so any value you store is immediately overwritten. Treat P as read-only.
How many machine cycles does a bank switch cost?
One MOV PSW,#data (or SETB/CLR on RS0/RS1) — a single instruction, typically one to two machine cycles, versus the many stack pushes a software context save would need.