In short: The 8051 has 111 instructions grouped into five functional classes — data transfer, arithmetic, logical, branching, and bit manipulation — and each executes in one or two machine cycles (12 or 24 oscillator periods on the classic core), so knowing the class, addressing mode, and cycle cost of each is what lets you write tight, deterministic firmware.
The Intel MCS-51 (8051) remains one of the most widely taught microcontroller architectures because its instruction set is small enough to memorize yet rich enough to teach every core CPU concept: accumulator-centric computation, multiple addressing modes, and single-bit Boolean processing. If you are preparing for an embedded systems interview or writing assembly for a legacy 8051 derivative (still shipping in automotive, keyboard controllers, and smart-card ICs), this categorized reference is the map you want. We assume you already understand the 8051 addressing modes; here we attach those modes to real opcodes and their timing.
How the five instruction classes fit together
The 8051 is an 8-bit accumulator machine. Almost every arithmetic or logical operation routes through the accumulator (A), while the 128 bytes of internal RAM, the four register banks (R0–R7), and the special function registers (SFRs) supply the operands. The genius of the design is its bit-addressable space: 128 directly addressable bits in RAM (20H–2FH) plus bits in many SFRs, which gives the 8051 a true Boolean processor few 8-bit rivals had.
1. Data transfer instructions
These move bytes without altering flags (except where the accumulator affects the parity bit). The workhorse is MOV, which supports immediate, direct, register, and register-indirect addressing. Movement to and from external memory uses the dedicated MOVX (external data, via DPTR or @Ri) and MOVC (code/program memory lookup — ideal for jump tables and character ROM).
MOV A,#55H— immediate load, 1 byte of operand, 1 machine cycle.MOV R0,A— register addressing, the fastest and most compact form.MOV A,@R1— register-indirect; R1 holds the RAM pointer.MOVX A,@DPTR— read external RAM; always 2 machine cycles because it drives the external bus.PUSH/POP— stack operations on direct addresses;XCHandXCHDswap data in a single step.
2. Arithmetic instructions
ADD, ADDC (add with carry), SUBB (subtract with borrow), INC, DEC, MUL AB, and DIV AB form this class. MUL and DIV are the only classic 8051 instructions that cost four machine cycles — a detail that trips up candidates asked why a multiply-heavy ISR blows its timing budget. DA A (decimal adjust) corrects BCD results after addition, which matters for clock and calculator firmware.
Key fact: On a 12 MHz classic 8051, one machine cycle = 1 µs. So MUL AB (8×8→16-bit) takes 4 µs, while ADD A,R0 finishes in 1 µs. Modern single-cycle cores (e.g. Silicon Labs EFM8) run the same opcodes up to 12× faster.
3. Logical instructions
Bitwise byte operations: ANL, ORL, XRL, CLR A, CPL A, plus the rotate family RL, RR, RLC, RRC and the nibble swap SWAP A. These are indispensable for masking port pins — e.g. ANL P1,#0FEH clears only bit 0 of Port 1 while leaving the other seven pins untouched. Rotate-through-carry instructions give you cheap serial-shift and ×2/÷2 operations.
4. Branching (program control) instructions
Here the target is the program counter. The 8051 offers three jump ranges, a distinction interviewers love: SJMP (short, ±127 bytes relative, 2 bytes), AJMP (absolute within a 2 KB page), and LJMP (long, full 64 KB). Conditional jumps include JZ/JNZ, JC/JNC, CJNE (compare-and-jump), and the compact loop primitive DJNZ (decrement and jump if not zero). Subroutines use ACALL/LCALL paired with RET, and RETI returns from interrupts while re-enabling the priority logic.
DJNZ R2,loop: the counter decrements each pass and the CPU falls through only when R2 reaches zero.5. Bit-manipulation (Boolean) instructions
This is the 8051's signature. The carry flag (C) acts as a single-bit accumulator. Instructions include SETB, CLR, CPL, ANL C,bit, ORL C,bit, MOV C,bit/MOV bit,C, and bit-conditional jumps JB, JNB, and JBC (jump and clear). You can therefore implement combinational logic directly: reading two switches on port bits and writing a computed output to an LED takes four Boolean instructions with no byte-wide masking at all.
Cycle-count quick reference
| Instruction | Class | Bytes | Machine cycles |
|---|---|---|---|
| MOV A,Rn | Data transfer | 1 | 1 |
| MOVX A,@DPTR | Data transfer | 1 | 2 |
| ADD A,direct | Arithmetic | 2 | 1 |
| MUL AB / DIV AB | Arithmetic | 1 | 4 |
| ANL A,Rn | Logical | 1 | 1 |
| LCALL addr16 | Branching | 3 | 2 |
| DJNZ Rn,rel | Branching | 2 | 2 |
| SETB bit / JB bit,rel | Bit | 2/3 | 1/2 |
Key fact: Of the 111 instructions, only two (MUL, DIV) exceed two machine cycles. That near-uniform timing is why 8051 assembly lends itself to cycle-accurate bit-banged protocols, and why vendors such as Keil (now part of Arm) ship cycle-count simulators rather than requiring hardware for timing validation.
When you port this knowledge to production work, remember that commercial toolchains — Keil C51, IAR Embedded Workbench, and Siemens/Mentor verification flows for 8051 soft cores on FPGA — all expose these same machine-cycle counts in their disassembly and profiler views. For the bigger picture of how an 8051 core is synthesized and verified on silicon, the design-services team at Avecas works with exactly these RTL-to-GDS flows.
Ready to write real 8051 firmware and debug it on hardware? Join the hands-on CourseTron Embedded Systems course and build timers, UART, and interrupt-driven projects from the instruction set up.
Frequently asked questions
How many instructions does the 8051 have?
The 8051 has 111 instructions encoded in 255 opcodes. They span five functional classes and operate across immediate, direct, register, register-indirect, and bit addressing modes.
Why do MUL and DIV take four machine cycles?
Both perform an 8-bit-by-8-bit operation producing a 16-bit result (product in A:B for MUL, quotient and remainder in A and B for DIV). The iterative shift-and-add/subtract hardware needs four cycles, versus one for a simple ADD. Budget this carefully inside interrupt service routines.
What is the difference between SJMP, AJMP, and LJMP?
SJMP uses an 8-bit signed relative offset (±127 bytes), AJMP jumps anywhere in the current 2 KB page using an 11-bit address, and LJMP provides a full 16-bit absolute target across the entire 64 KB code space. Assemblers often pick the shortest form automatically.
What makes the 8051 a "Boolean processor"?
It can address 128 RAM bits plus many SFR bits individually and run logical operations with the carry flag as a one-bit accumulator. You can compute combinational logic on I/O pins directly, something most 8-bit rivals could only emulate with byte masking. See our 8051 timers and interrupts guide for how this applies to real peripherals.