In short: Neuromorphic chips such as Intel's Loihi fuse memory and compute and fire only when data arrives as spikes, so a workload that is sparse and event-driven can run at a tiny fraction of the energy a GPU would burn doing the same inference.
Every deep-learning accelerator you have met — a GPU, a systolic TPU, an analog crossbar — shares one habit: it computes on a clock, moving dense tensors whether or not the numbers are interesting. Neuromorphic hardware breaks that habit. It borrows the brain's trick of staying silent until something happens, then communicating with brief, discrete spikes. When almost nothing is happening, almost no energy is spent. This article explains how spiking neural network (SNN) silicon actually works, why the energy numbers are so striking, and where the approach wins and loses in practice.
What makes a neuron "spiking"
A conventional artificial neuron outputs a continuous activation every forward pass. A spiking neuron instead maintains an internal membrane potential that integrates incoming current over time. The workhorse model is Leaky Integrate-and-Fire (LIF): incoming spikes add charge, the potential leaks away slowly, and when it crosses a threshold the neuron emits a single spike and resets. Information lives in when and how often neurons fire, not in a dense floating-point vector.
That temporal, binary signalling is the whole game. A spike is a 1-bit event with an address, so the hardware never multiplies activations — it simply adds a synaptic weight to a membrane counter whenever a spike arrives. No spike, no work. On natural data that is bursty and sparse (a DVS event camera, an audio keyword, a radar return), 90–99% of neurons stay quiet in any given time step.
Event-driven compute and the address-event bus
To exploit sparsity, the chip must route spikes without a global clock dictating every move. Neuromorphic processors use Address-Event Representation (AER): each spike is a short packet carrying the source neuron's address and a timestamp, pushed onto an asynchronous network-on-chip only when it occurs. Cores wake, update the targeted membranes, and go idle again.
This is why neuromorphic designs co-locate memory and compute. In Loihi, each of 128 cores holds its own SRAM for synaptic weights and neuron state, so a spike update is a local read-add-write with no trip to external DRAM. Avoiding that off-chip memory traffic is the single biggest reason the energy per inference collapses — DRAM access can cost 100× the energy of the arithmetic itself.
Key fact: Intel's Loihi 2 (Intel 4 process) packs up to ~1 million neurons and ~120 million synapses per chip, and its asynchronous fabric lets a core consume essentially zero dynamic power while its neurons are silent.
Why the energy numbers are so good
Three mechanisms stack to produce the headline efficiency:
- Sparsity: work scales with the number of spikes, not the number of neurons. A keyword spotter that is quiet 99% of the time does 1% of the arithmetic.
- In-memory compute: weights sit beside the neuron, eliminating the dominant DRAM energy term.
- Event-driven clocking: no spike means no toggling transistors, so static leakage dominates the idle budget rather than wasted dynamic switching.
Published benchmarks show the pattern clearly. On keyword spotting and gesture recognition from event-camera data, Loihi-class systems have reported one to two orders of magnitude lower energy per inference than an equivalent task on a GPU, with comparable accuracy. The win is largest precisely when the input is sparse and temporal — and shrinks toward zero when it is dense.
| Attribute | GPU (dense ANN) | Neuromorphic SNN |
|---|---|---|
| Data unit | FP16/INT8 tensor | 1-bit spike + address |
| Timing | Synchronous clock | Asynchronous, event-driven |
| Memory | Off-chip HBM/DRAM | On-core SRAM beside compute |
| Idle power on sparse input | High (clock still runs) | Near-zero dynamic |
| Best-fit workload | Dense vision, LLMs | Sparse, streaming, temporal |
The training problem and the toolchain
The hard part is not the silicon — it is getting a trained network onto it. Spikes are non-differentiable, so you cannot backpropagate through a threshold directly. Two routes dominate. The first is surrogate-gradient training, where the discontinuous spike is replaced by a smooth proxy during the backward pass (frameworks like snnTorch, Norse, and Intel's Lava do this). The second is ANN-to-SNN conversion: train a normal ReLU network, then map activations to firing rates. Mature commercial EDA flows from Synopsys, Cadence, and Siemens EDA are not yet neuromorphic-native, so most SNN silicon today is designed with standard RTL-to-GDSII flows while the mapping and quantisation happen in these research toolchains above the hardware.
Key fact: Because a spike carries one bit, routing and SRAM are the area/power bottlenecks — not multipliers. Designers of SNN chips spend their silicon budget on fan-out and local memory, the opposite of a GPU's multiplier-heavy datapath.
Where it fits — and where it does not
Neuromorphic hardware is not a drop-in GPU replacement. It shines at always-on edge sensing: keyword wake-up, event-camera vision, biosignal and anomaly detection, robotic reflex loops, and adaptive control where latency and microwatt budgets matter more than peak throughput. It struggles on dense, high-precision workloads — large language models, high-resolution dense CNNs — where there is no sparsity to exploit and the spike-encoding overhead becomes pure cost. The honest framing is that it is a complementary accelerator for a specific shape of problem, closely related to the mixed-signal approaches we cover in our analog AI accelerator explainer and the on-device tradeoffs in our edge AI inference chips guide.
If you are evaluating this class of hardware for a product, pair the architecture study with real design-flow experience. Teams building custom AI silicon often prototype the digital portion through a conventional ASIC flow before committing — the kind of end-to-end RTL-to-GDSII work handled by design-services groups such as Avecas VLSI design services.
Want to design accelerators like Loihi hands-on? Our CourseTron AI Hardware track walks you from LIF neurons to silicon-aware SNN mapping with real lab flows.
Frequently asked questions
Is a spiking neural network always more efficient than a GPU?
No. The advantage comes entirely from sparsity and event-driven idling. On dense workloads where nearly every neuron fires every step, an SNN can be less efficient than a well-utilised GPU because of spike-encoding and routing overhead. The gains appear on sparse, temporal, streaming data.
What is Intel Loihi?
Loihi is Intel Labs' research neuromorphic processor. Each chip has many asynchronous cores, each with local SRAM for weights and neuron state, connected by an address-event mesh. Loihi 2 scales to roughly a million neurons per chip and is programmed through the open-source Lava framework.
How are SNNs trained if spikes aren't differentiable?
Two main methods: surrogate-gradient descent, which substitutes a smooth function for the spike during backpropagation, and ANN-to-SNN conversion, which trains a standard network and maps its activations onto firing rates. Tools like snnTorch, Norse, and Lava implement these.
Can I use standard EDA tools to design neuromorphic chips?
Mostly yes for the digital implementation — Synopsys, Cadence, and Siemens EDA RTL-to-GDSII flows build the cores and interconnect. The neuromorphic-specific part (neuron models, spike mapping, quantisation) lives in research frameworks layered above the hardware rather than in mainstream commercial EDA today.