RTL Design & Verilog Interview Questions

Blocking (=) executes sequentially; non-blocking (<=) schedules RHS and assigns at the time-step end, modeling parallel updates. Use non-blocking for sequential (always_ff) and blocking for combinational (always_comb).

A latch is level-sensitive (transparent when enabled); a flip-flop is edge-triggered. Unintended latches from incomplete if/case are a common RTL bug.

Assign every output in all branches: default assignment at the top of always_comb, complete if-else, and a default in case statements.

A Finite State Machine has states, transitions, outputs. Encodings: binary (fewest flops), one-hot (fast decode, FPGA-friendly), gray (low glitch/power). Moore outputs depend on state only; Mealy on state+inputs.

CDC passes a signal between async clocks, risking metastability. Single bits use 2-flop synchronizers; buses use gray-code, handshakes, or async FIFOs.

wire is a continuous connection (assign/output); reg holds a value in procedural blocks. reg is not always a hardware register. SystemVerilog logic unifies both.

A module with overridable parameters (width, depth) enabling reusable, scalable IP — one design serves many configurations without duplication.

generate (genvar) elaborates hardware structurally at compile time (replicating instances). A procedural for loop describes repeated behavior inside an always block.

SystemVerilog intent-specific blocks: always_comb for combinational, always_ff for edge-triggered sequential, always_latch for latches. They let tools check that your code matches intent, catching accidental latches.

Synchronous reset is sampled on the clock edge (cleaner timing, needs a running clock). Asynchronous reset acts immediately regardless of clock (faster, but needs reset-recovery/removal timing and synchronized de-assertion).

RTL itself does not have setup/hold (that is post-synthesis timing), but poor RTL (long combinational paths, missing pipelining) causes violations later. Prevent by pipelining critical paths and balancing logic depth.

case does exact matching. casez treats Z (and ?) as dont-care. casex treats both X and Z as dont-care — casex is dangerous in simulation (X masking real bugs) and generally discouraged; prefer case or casez.

One-hot uses one flip-flop per state (only one bit high). FPGAs have abundant flops and it gives fast, simple next-state decode logic, improving timing — preferred over binary in FPGA designs.

Moore outputs depend only on the current state (registered, glitch-free, one cycle later). Mealy outputs depend on state and inputs (faster response, fewer states, but can glitch). Choice depends on timing and output requirements.

Lint (e.g., Spyglass) statically checks RTL for issues like latches, multi-driven signals, incomplete sensitivity, CDC problems, and unsynthesizable constructs — catching bugs before synthesis.

$display prints once when executed. $monitor prints automatically whenever any of its listed variables change. Both are testbench/debug tasks, not synthesizable.