FPGA Interview Questions & Answers

FPGA is reconfigurable, fast time-to-market, low NRE — for prototyping/low-medium volume. ASIC is custom-fabricated, higher performance, lower unit cost/power at volume, but high NRE.

CLBs/LABs (LUTs + flip-flops), programmable interconnect, Block RAM, DSP slices, clock management (PLL/MMCM), configurable I/O, and often hard processors and transceivers.

A Look-Up Table is a small SRAM storing the truth table of any N-input logic function (typically 4-6 inputs) — the basic combinational element, combined with flops for arbitrary logic.

RTL design → synthesis → implementation (translate, map, place & route) → timing analysis with constraints → bitstream generation → device configuration. Tools: Vivado, Quartus.

Constraints (clock period, I/O delays, false/multicycle paths) tell tools the requirements so P&R can meet them and STA can verify. Missing constraints cause hardware failures.

A flop sampling data that violates setup/hold enters an undefined state. Handle with multi-flop synchronizers for single bits, async FIFOs/handshakes for buses.

Block RAM uses dedicated memory blocks — efficient for larger memories. Distributed RAM uses LUTs as small fast memories — good for small buffers but consumes logic.

Reprogramming part of the FPGA while the rest runs — enabling time-multiplexed functions, lower area/power, and field updates (SDR, accelerators).

Setup (max-delay) failures are fixed by reducing logic levels, pipelining, or relaxing the clock. Hold (min-delay) failures are usually fixed automatically by the tool inserting delay; persistent ones indicate CDC or constraint issues.

FPGAs divide the die into clock regions served by dedicated clock buffers (BUFG/BUFR). Placing related logic in the same region and using global buffers minimizes clock skew and meets timing.

A synchronous FIFO has the same read/write clock. An asynchronous FIFO crosses two clock domains, using gray-coded pointers and synchronizers to safely pass data and generate full/empty flags.

Dedicated hardware blocks (e.g., DSP48) performing multiply-accumulate efficiently — used for filters, FFTs, and AI inference, far faster and lower-power than building multipliers from LUTs.

RTL (behavioral) simulation verifies functionality with zero/unit delays. Timing (post-implementation) simulation uses real gate and routing delays (SDF back-annotation) to verify the design works at speed.

HLS (e.g., Vitis HLS) converts C/C++/SystemC into RTL, letting engineers design hardware accelerators at a higher abstraction with pragmas controlling parallelism, pipelining, and interfaces.

A pre-designed, verified reusable block (memory controller, PCIe, Ethernet MAC, FFT). Using vendor/3rd-party IP saves development time and reduces risk versus designing from scratch.

Static (leakage) and dynamic (switching) power. Reduce via clock gating, lower toggle rates, efficient resource use, BRAM over distributed RAM, lower voltage/frequency, and disabling unused blocks.