Embedded Systems Interview Questions & Answers

A microprocessor (Cortex-A, x86) needs external memory/peripherals — for computers/phones. A microcontroller (Cortex-M, AVR) integrates CPU+RAM+flash+peripherals — for embedded control.

An RTOS gives task scheduling, IPC, and timing guarantees. Needed for multiple concurrent tasks with deadlines. Bare-metal suffices for simple loops. Examples: FreeRTOS, Zephyr.

A mutex has ownership and protects shared resources (only the locker unlocks; supports priority inheritance). A semaphore is a signaling/counting mechanism without ownership.

An interrupt pauses execution for an urgent event; the ISR handles it. Keep ISRs short, avoid blocking, and defer heavy work to tasks via semaphore/queue.

volatile tells the compiler a variable can change outside normal flow (HW registers, ISR globals), preventing optimization that caches stale values — a classic embedded bug source.

A high-priority task blocks on a resource held by a low-priority task preempted by a medium one. Solved by priority inheritance or priority ceiling protocols.

SPI: full-duplex, 4 wires, fast, one SS per slave. I2C: 2 wires with addressing, many devices, slower, half-duplex. SPI for speed; I2C for many low-speed peripherals.

Direct Memory Access transfers data between peripheral and memory without CPU, freeing it and enabling high-throughput, low-latency transfers (ADC, SPI/UART bursts).

RAM (SRAM) is volatile working memory for variables/stack. Flash/ROM is non-volatile, storing code and constants. The .data section is copied from flash to RAM at startup; .bss is zero-initialized in RAM.

Startup (crt0/reset handler) sets the stack pointer, copies .data from flash to RAM, zeroes .bss, initializes the C runtime and vector table, then calls main(). On MCUs it also configures clocks.

A hardware timer that resets the system if not periodically refreshed (kicked), recovering from hangs/lockups. Critical for reliability in unattended embedded systems.

Polling repeatedly checks a status flag (simple, wastes CPU, predictable). Interrupt-driven responds only on events (efficient, lower latency, more complex). Choose based on event rate and power needs.

Endianness is byte ordering of multi-byte values. Big-endian stores MSB first; little-endian LSB first (ARM/x86). It matters for data exchange between systems, network protocols, and memory-mapped access.

Peripheral registers are accessed as specific memory addresses, so reads/writes to those addresses control hardware. In C, accessed via volatile pointers to the register base + offsets.

Hard real-time: missing a deadline is catastrophic (airbags, pacemakers). Soft real-time: occasional misses degrade quality but are tolerable (video streaming). Determines scheduling rigor.

The stack grows beyond its allocated region, corrupting adjacent memory. Detected via stack canaries/painting, MPU guard regions, RTOS high-water-mark monitoring, and linker-defined limits.