DFT Interview Questions & Answers

DFT adds structures (scan, BIST, boundary scan) that make a chip easier to test for manufacturing defects, improving fault coverage and yield while reducing test cost.

It replaces normal flops with scan flops (mux-D) stitched into shift chains. Patterns shift in, one capture clock applies, responses shift out and compare against expected.

Automatic Test Pattern Generation creates input patterns to detect faults (stuck-at, transition, path-delay), targeting maximum coverage with minimum patterns.

Models a node permanently stuck at 0 or 1. Most common model; aim for 99%+ coverage. Others: transition-delay, path-delay, bridging.

Built-In Self-Test embeds test circuitry on-chip. MBIST tests memories; LBIST tests logic with an LFSR generator and MISR compressor — reducing ATE dependence.

IEEE 1149.1 adds a scan cell at each I/O, accessed via the TAP (TDI/TDO/TMS/TCK), enabling board-level interconnect test and in-system programming.

EDT/MaxTest reduce test data and time via a decompressor feeding many internal chains from few ATE channels plus an output compactor — cutting test cost 10-100x.

After placement, scan flops are reconnected in a physically optimal order to minimize scan-wire length and congestion while preserving the logical chain.

Controllability is the ability to set an internal node to a desired value from inputs; observability is the ability to propagate a node value to an observable output. DFT improves both for testability.

Testing at the chips functional clock frequency to catch timing/delay defects (transition and path-delay faults) that slow-speed stuck-at tests miss. Uses launch-on-capture or launch-on-shift.

An LFSR (Linear Feedback Shift Register) generates pseudo-random test patterns. A MISR (Multiple Input Signature Register) compresses many output responses into a single signature compared against the golden value.

Fault coverage = detected faults / total faults. Test coverage = detected faults / testable faults (excludes untestable/redundant faults). Test coverage is usually the more meaningful signoff metric.

Higher compression (more internal chains per channel) reduces test time/data but can lower coverage on some patterns and increase routing/X-handling complexity. Engineers balance ratio vs coverage.

X sources (uninitialized memories, non-scan flops, bus contention) corrupt the MISR signature and mask faults. Handled with X-masking, X-bounding, or making sources controllable.

Combinational ATPG assumes full scan (all flops controllable/observable), simplifying to combinational test generation. Sequential ATPG handles non-scan/partial-scan designs, requiring multi-cycle pattern reasoning — far more complex.

IEEE 1500 adds a test wrapper around embedded cores/IP so each can be tested in isolation and integrated into the SoC test plan — essential for core-based and hierarchical DFT.