ASIC Verification & UVM Interview Questions

UVM is a standardized SystemVerilog class library for reusable, scalable verification environments. It provides agents, scoreboards, factory, and config_db, and is vendor-independent across VCS, Questa, and Xcelium.

sequence_item (transaction), sequence (generates items), sequencer (arbitrates), driver (drives DUT), monitor (samples DUT), agent (bundles them), scoreboard (checks), env (container), and test (configures/runs).

A function executes in zero time, cannot block, and returns a value. A task can consume time and contain delays. Use functions for computation, tasks for timed stimulus.

== is logical equality, returning X if any bit is X/Z. === is case equality, comparing X/Z literally and always returning 0 or 1 — used to check exact 4-state values.

Code coverage measures which RTL lines/branches ran (automatic). Functional coverage measures whether intended features/scenarios were tested (manual covergroups). Both are needed for confidence.

The factory creates objects by type/instance with override capability, letting you swap base components with derived ones (e.g., error injection) at runtime without editing the testbench — central to reuse.

build (top-down), connect (bottom-up), end_of_elaboration, start_of_simulation, run (time-consuming, with reset/configure/main/shutdown sub-phases), then extract/check/report/final.

A virtual sequence has no driver; it coordinates multiple sequencers to orchestrate complex multi-interface scenarios, e.g., synchronizing traffic across agents in an SoC testbench.

uvm_component is quasi-static, exists for the whole simulation, has phases and a hierarchy position (driver, monitor, env). uvm_object is transient data (transactions, sequences) created/destroyed dynamically.

config_db is a hierarchical database to pass configuration (virtual interfaces, settings) from test/env down to components using set()/get() with string paths — decoupling configuration from construction.

An active agent drives stimulus (has sequencer+driver+monitor). A passive agent only monitors (monitor only) — used to observe interfaces without driving, e.g., on the DUT output side.

SystemVerilog Assertions check design properties. Immediate assertions are procedural, checked like an if-statement. Concurrent assertions are clocked, checking temporal properties over time (e.g., req must be followed by ack within 3 cycles).

fork-join waits for all spawned threads; join_any waits for the first to finish; join_none does not wait and continues immediately. Used to model concurrent stimulus.

A scoreboard receives transactions from monitors (often via analysis ports/FIFOs), computes or stores expected results (reference model), and compares against actual DUT output to flag mismatches.

Instead of writing directed tests, you define random variables with constraints (rand + constraint blocks) so the solver generates legal, diverse stimulus automatically — covering corner cases directed tests miss.

bit is 2-state (0,1) — faster simulation, used for testbench counters. logic is 4-state (0,1,X,Z) — models real hardware including unknowns and high-Z, used for DUT-facing signals.