Analog IC Design Interview Questions & Answers

Single-stage (telescopic/folded-cascode) is fast with good frequency response but limited swing/gain. Two-stage adds a gain stage for higher gain and swing, needing Miller compensation for stability.

For a single-pole amp, GBW equals the unity-gain frequency and is roughly constant — so higher closed-loop gain means lower bandwidth.

The Miller cap splits the poles (pole splitting), lowering the dominant pole and raising the second, ensuring phase margin and stability at the cost of bandwidth.

Common-Mode Rejection Ratio = differential gain / common-mode gain (in dB). High CMRR rejects noise/supply interference common to both inputs.

It sums a CTAT voltage (BJT VBE) with a PTAT voltage (scaled thermal voltage) to produce ~1.2V nearly independent of temperature — used for ADCs, regulators, bias.

A PLL uses a VCO to lock frequency/phase and can multiply frequency. A DLL uses a delay line to align phase only — more stable (no VCO jitter accumulation) but cannot multiply frequency.

Flash: fastest, high power/area. SAR: low power, 8-16 bits. Sigma-Delta: high resolution, low speed (oversampling). Pipeline: high speed at medium-high resolution.

In saturation, higher Vds slightly shortens the channel, raising current — a finite output resistance (Early effect analog), modeled by lambda. It limits intrinsic gain.

Slew rate is the maximum dVout/dt the op-amp can deliver, limited by the bias current charging the compensation/load capacitor (SR = I/C). It causes large-signal distortion if exceeded.

Phase margin is how far the loop phase is from -180 degrees at unity-gain frequency. Adequate margin (typically >60 degrees) ensures stability and limits ringing/overshoot in the step response.

A current mirror copies a reference current to one or more outputs using matched transistors. Used for biasing, active loads (high gain), and current distribution. Cascoding improves output impedance and matching.

Thermal noise sampled onto a capacitor has total power kT/C (independent of resistance). It sets the fundamental noise floor in switched-capacitor circuits and ADCs — larger caps reduce it at the cost of area/power.

Input offset is the differential voltage needed to zero the output, caused by device mismatch. Reduced by larger devices, careful layout (common-centroid), and techniques like chopping or auto-zeroing.

Class A conducts the full cycle (linear, low distortion, inefficient). Class B uses push-pull, each device half the cycle (efficient but crossover distortion). Class AB biases slightly on to remove crossover distortion — the common compromise.

Matched devices (current mirrors, diff pairs) must behave identically. Common-centroid layout interdigitates them around a shared center so process/temperature gradients cancel, minimizing mismatch and offset.

A MOSFET enters saturation when Vds > Vgs - Vth, where current is roughly constant (ideal amplifier region). Triode/linear region (Vds small) acts like a voltage-controlled resistor (used for switches).