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Static Timing Analysis (STA) Basics — Setup, Hold, and Skew Explained

Coursetron Admin

Thu, 03 Sep 2026

Static Timing Analysis (STA) Basics

STA is the math behind every chip’s timing closure. Unlike simulation, STA does not need test vectors — it checks every timing path against setup and hold constraints. Master STA and you are 70% of the way to a PD/signoff job.

The Two Golden Rules

Setup: Data must arrive at the capture flop before the clock edge, by at least Tsetup. Slack = required − arrival.
Hold: Data must remain stable after the clock edge, by at least Thold. Slack = arrival − required.

Timing Path Types

1. Reg-to-reg (most common)
2. Input-to-reg (constrained by input delay)
3. Reg-to-output (constrained by output delay)
4. Input-to-output (combinational, max_delay)

Key Concepts

• Clock skew: Difference in clock arrival times. Helps setup, hurts hold.
• Clock uncertainty: Pre-CTS placeholder for skew + jitter
• OCV (On-Chip Variation): AOCV / POCV / SOCV at advanced nodes
• Multicycle path: Tells STA the path takes N cycles, not 1
• False path: Tells STA to ignore (async crossing handled by sync)

Common SDC Commands

create_clock -name clk -period 2.0 [get_ports clk]
set_input_delay -max 0.5 -clock clk [get_ports din]
set_output_delay -max 0.5 -clock clk [get_ports dout]
set_multicycle_path 2 -setup -from FF1 -to FF2
set_false_path -from FF_async -to FF_sync

Fix Strategies

• Setup violation: upsize cells, restructure logic, useful skew, pipeline
• Hold violation: insert delay buffers, downsize cells, adjust skew

Tools

Synopsys PrimeTime (industry standard signoff), Cadence Tempus.

Learn STA Hands-On

STA is covered in depth in our Physical Design Course with PrimeTime labs.