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Physical Design Interview Questions — Complete Guide for VLSI Engineers | CourseTron 2026

Coursetron Admin

Thu, 03 Sep 2026

Why Physical Design Interviews Are Different

Physical design (PD) interviews test something most other VLSI interviews do not: whether you understand the consequences of every step in the RTL-to-GDSII flow. Anyone can recite the stages — floorplanning, placement, clock tree synthesis, routing, signoff — but interviewers quickly probe what happens when a stage goes wrong. Why did congestion explode after placement? Why did hold violations appear only after CTS? Why does the design pass timing but fail IR drop? The engineers who get hired are the ones who can trace cause and effect across the flow, not just name the tools.

This guide covers the question patterns that recur in PD interviews across product companies and service companies, with worked answers you can adapt to your own project experience.

How a Typical PD Interview Is Structured

• Flow walkthrough: you describe your project block — cell count, frequency, technology node, utilization — and the interviewer drills into decisions you made.
• Concept rounds: STA fundamentals, CTS trade-offs, routing rules, low-power techniques (UPF, power gating, multi-Vt).
• Debug scenarios: "Your design fails hold after routing — what do you check first?" These reward structured thinking over memorised answers.
• Signoff awareness: DRC/LVS, IR drop, EM, antenna checks — even junior candidates are expected to know what each check protects against.

Core Questions and How to Answer Them

Q1. What do you consider while deciding a floorplan?

Talk in priorities, not a list. Start with macro placement: macros go near the boundary or grouped by connectivity, with their pins facing the standard-cell area so routing does not detour around them. Keep channels between macros wide enough for the routes and power straps that must pass through, and avoid notches that trap standard cells. Then cover pin placement aligned with neighbouring blocks, a starting utilization low enough (often somewhere around 60–75 percent, depending on node and congestion) to leave room for optimisation cells, and a power grid planned before placement, not after. Close with how you validated it: congestion map, early global route, and trial timing.

Q2. Why are hold violations often discovered after CTS, and how do you fix them?

Before CTS the tool typically treats clocks as ideal, so launch and capture edges arrive simultaneously and hold looks clean. CTS builds the real tree, introducing skew: if the capture flop's clock arrives later than the launch flop's, hold margin shrinks on that path. Fixes, in the usual order of preference: let the tool insert hold buffers/delay cells on the data path, use skew balancing or useful-skew adjustments in the tree, and only rarely resize cells — downsizing to slow a data path can hurt setup on shared segments. Mention that hold must be fixed across all corners, because a path safe at the slow corner can violate at the fast corner.

Q3. Setup and hold — which is more dangerous, and why?

A setup violation is frequency-dependent: the chip may still work at a lower clock speed. A hold violation is frequency-independent — the race between data and clock exists at any speed, so a hold failure usually means dead silicon. That is why hold is signed off with extra pessimism (additional uncertainty, multiple corners, OCV/AOCV derates) and why hold fixes are never "waived to be checked later".

Q4. Placement is done but congestion is high in one region. What do you do?

Show a debug sequence: check whether a macro channel is too narrow or macro pins face the wrong way; look for a locally dense logic cone (a wide mux structure or memory interface) that can be spread with placement blockages or density screens; verify the region is not sitting over a routing blockage or dense power strap; consider re-ordering scan chains, since a poorly stitched scan chain adds thousands of unnecessary routes; and if all else fails, revisit the floorplan. Saying "I would just increase the die size" without exploring these first is a red flag.

Q5. What does IR drop analysis check, and what happens if you ignore it?

IR drop analysis verifies that every cell receives supply voltage within a budget (static for average current, dynamic for switching peaks). Excessive drop slows cells — timing that passed STA at nominal voltage can fail in silicon — and severe local drop can cause functional failure. Typical mitigations: strengthen the grid in hot regions, add decap cells near aggressors, spread simultaneously switching logic, and reduce clock-gating clusters that fire together.

Q6. Explain antenna violations and two fixes.

During fabrication, a long metal segment connected to a transistor gate collects charge from plasma etching before the full path to diffusion exists; the accumulated charge can damage the thin gate oxide. Fixes: insert a jumper to a higher metal layer so the long segment is no longer tied to the gate during lower-layer processing, or add an antenna diode that safely discharges the node. Knowing why the rule exists — not just the fix — is what interviewers listen for.

Preparation Checklist

• Be able to quote your own project numbers: node, standard-cell count, macro count, target frequency, utilization, worst slack before and after each stage.
• Practise reading a timing report aloud — arrival, required, slack, and which segment (clock network, cell delay, net delay) dominates.
• Revise one low-power flow end to end: UPF intent, isolation, level shifters, retention, and how each is verified.
• Prepare one honest failure story — a violation you debugged the wrong way first — and what the correct diagnosis taught you.

If you need structured revision of the underlying flow before interview practice, you can browse all courses on CourseTron, where physical design sits alongside verification, DFT and related tracks in our online electronics classes.

Frequently Asked Questions

How many projects should a fresher discuss in a PD interview?

One block done thoroughly beats three done superficially. Interviewers spend most of the time on a single design, so pick the block whose every number and decision you can defend.

What salary can a physical design engineer expect?

Compensation varies widely with company type, node experience and location. In India, entry-level PD roles have indicatively ranged from a few lakhs to low double-digit lakhs per annum, with senior signoff-capable engineers earning substantially more — treat any specific figure as a rough guide, not a promise.

Do I need scripting skills for PD interviews?

Yes, increasingly so. Tcl is the working language of the major P&R and STA tools, and many interviews include a small task such as parsing a timing report or filtering paths. Basic Tcl plus some Python or shell scripting is a realistic baseline.