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Analog Design Interview Questions — Complete Guide for VLSI Engineers | CourseTron 2026

Coursetron Admin

Thu, 03 Sep 2026

Why Analog Design Interviews Feel Different

Analog interviews are intuition tests disguised as technical rounds. A digital design candidate can often reason from truth tables and timing reports; an analog candidate is handed a marker, drawn a two-transistor circuit, and asked "what happens if this node moves up by 100 mV?" There is no simulator to hide behind. Interviewers at semiconductor companies deliberately strip problems down to hand-analysis level because they want to see whether you can predict circuit behaviour before SPICE confirms it. That skill — estimating gain, swing, bandwidth, and noise on the back of an envelope — is what this guide helps you rehearse.

The Topics Interviewers Keep Returning To

Across analog and mixed-signal interviews, the same core areas appear again and again:

• MOSFET operation: regions of operation, square-law vs. velocity-saturated behaviour, channel-length modulation, body effect.
• Single-stage amplifiers: common-source, common-gate, source follower — gain, input/output impedance, and when to use each.
• Current mirrors and biasing: simple vs. cascode mirrors, headroom trade-offs, supply-independent bias.
• Differential pairs and op-amps: CMRR, offset, slew rate, two-stage topologies.
• Feedback and stability: loop gain, phase margin, Miller compensation, the right-half-plane zero.
• Noise and mismatch: thermal vs. flicker noise, Monte Carlo thinking, layout matching techniques.

Sample Questions with Strong Answers

Q1. Why do we bias amplifying transistors in saturation rather than triode?

Strong answer: In saturation the drain current is largely independent of Vds, so the device behaves as a voltage-controlled current source with high output resistance — exactly what an amplifier needs to develop large voltage gain (roughly gm·ro for a single stage). In triode the channel acts like a gate-controlled resistor: output resistance collapses, gain drops, and the stage becomes strongly nonlinear over its swing. A follow-up interviewers love: mention that "saturation" in a MOSFET is the opposite naming convention from a BJT, where saturation is the low-gain region.

Q2. A simple current mirror copies current inaccurately. What are the error sources, and how does a cascode help?

Strong answer: Three main errors: (1) channel-length modulation — the output device sees a different Vds than the diode-connected reference, so the copied current shifts with output voltage; (2) threshold-voltage mismatch between the two devices; (3) finite output resistance loading whatever the mirror drives. A cascode stacks a second transistor on the output branch, multiplying output resistance by roughly gm·ro and holding the mirror device's Vds nearly constant, which suppresses the modulation error. The price is headroom: each cascode device consumes an extra saturation voltage, which is why low-voltage designs use wide-swing cascode biasing. Mentioning that trade-off unprompted signals real design experience.

Q3. What is phase margin, and why is a two-stage op-amp Miller-compensated?

Strong answer: Phase margin is 180° minus the phase shift of the loop gain at the frequency where its magnitude crosses unity; around 60° is a common target because it gives fast settling without excessive ringing. A two-stage op-amp has two comparable low-frequency poles, which alone would leave near-zero margin. The Miller capacitor across the second stage performs pole splitting — pushing the dominant pole down and the second pole up — restoring margin. The subtlety worth volunteering: the Miller capacitor also creates a right-half-plane zero through its feed-forward path, which degrades phase; a nulling resistor in series with the capacitor moves or cancels that zero.

Q4. Compare thermal noise and flicker noise. How would you reduce each?

Strong answer: Thermal noise is white, arises from carrier agitation in the channel, and scales inversely with gm — so you reduce it by burning more current or widening the device. Flicker (1/f) noise comes from carrier trapping at the gate-oxide interface, dominates at low frequencies, and scales inversely with gate area — so you use large W·L input devices, prefer PMOS inputs (typically lower 1/f in many processes), or sidestep it architecturally with chopping or correlated double sampling. Knowing the corner frequency concept — where the two contributions are equal — rounds out the answer.

Q5. What does the gm/Id methodology give you that the square-law model does not?

Strong answer: In modern short-channel processes the square-law equations are quantitatively wrong, especially in moderate inversion where many low-power designs actually operate. The gm/Id approach treats transconductance efficiency as the design variable, using lookup curves generated from the foundry models themselves. It lets you trade speed (fT) against efficiency continuously across weak, moderate, and strong inversion, and it makes sizing systematic instead of iterative guessing in the simulator.

Q6. Why use a differential pair at the input of an op-amp?

Strong answer: It rejects common-mode disturbances — supply bounce, substrate noise, temperature drift — because they move both sides equally and cancel at the differential output, quantified by CMRR. It also cancels even-order distortion and gives a well-defined zero-input condition. A sharp follow-up is what limits CMRR in practice: mismatch between the pair and the finite output resistance of the tail current source.

Preparation Checklist That Actually Works

• Re-derive the gain and output resistance of the five basic stages by hand until it takes under a minute each.
• Practise "what changes if…" perturbation questions aloud — temperature up, supply down, W doubled.
• Design one complete two-stage op-amp on paper: sizing, bias, compensation, and expected phase margin.
• Be ready to sketch layout matching techniques: common-centroid, interdigitation, dummy devices.
• Review any project on your resume down to device-level decisions — interviewers probe your own work hardest.

Structured practice beats passive reading here. If you want to rebuild fundamentals before drilling questions, CourseTron's online electronics classes cover the device physics and circuit analysis these interviews assume, and you can browse all courses to find analog, mixed-signal, and layout tracks that match your target role.

Frequently Asked Questions

How much device physics do I really need?

Enough to explain behaviour, not derive it from Schrödinger's equation. You should comfortably discuss threshold voltage, mobility degradation, channel-length modulation, and body effect, and connect each to a circuit consequence. Fresh graduates get more physics questions; experienced candidates get more architecture and trade-off questions.

Will I be asked to solve equations exactly?

Rarely. Interviewers want proportionality reasoning: gain scales with gm·ro, noise power with kT/C, bandwidth with gm/C. Getting the dependencies and rough magnitudes right matters far more than exact arithmetic.

What do analog design roles typically pay?

Compensation varies widely with country, company type, and process-node experience, so treat any figure as indicative only. Analog and mixed-signal skills are scarce relative to demand, and experienced designers generally command salaries at the upper end of semiconductor engineering ranges in their region — but verify current numbers for your specific market before negotiating.